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| author | Jing Liu <jing2.liu@intel.com> | 2022-02-16 22:04:30 -0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-03-15 11:50:50 +0100 |
| commit | 0f17f6b30f3b051f0f96ccc98c9f7f395713699f (patch) | |
| tree | 4f48b710cb1a2e41b6621cc02599a0930d26c874 /target/i386/cpu.c | |
| parent | 19db68ca68a78fa033a21d419036b6e416554564 (diff) | |
| download | qemu-0f17f6b30f3b051f0f96ccc98c9f7f395713699f.zip qemu-0f17f6b30f3b051f0f96ccc98c9f7f395713699f.tar.gz qemu-0f17f6b30f3b051f0f96ccc98c9f7f395713699f.tar.bz2 | |
x86: Add XFD faulting bit for state components
Intel introduces XFD faulting mechanism for extended
XSAVE features to dynamically enable the features in
runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
as 1, it indicates support for XFD faulting of this
state component.
Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-5-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/cpu.c')
| -rw-r--r-- | target/i386/cpu.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 505ee28..79e24bb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5496,7 +5496,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, const ExtSaveArea *esa = &x86_ext_save_areas[count]; *eax = esa->size; *ebx = esa->offset; - *ecx = esa->ecx & ESA_FEATURE_ALIGN64_MASK; + *ecx = esa->ecx & + (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); } } break; |