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| author | Michael Tokarev <mjt@tls.msk.ru> | 2023-07-14 14:23:51 +0300 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-07-25 17:14:07 +0300 |
| commit | 8b81968c1cf351430dad66a1b36420f431243842 (patch) | |
| tree | 1ba710e8ade4b755d15bd89b8157c0d8cd4d9b01 /target/hppa | |
| parent | 673d8215415dc0c13e96b8d757102d942916d1b2 (diff) | |
| download | qemu-8b81968c1cf351430dad66a1b36420f431243842.zip qemu-8b81968c1cf351430dad66a1b36420f431243842.tar.gz qemu-8b81968c1cf351430dad66a1b36420f431243842.tar.bz2 | |
other architectures: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/hppa')
| -rw-r--r-- | target/hppa/cpu.h | 4 | ||||
| -rw-r--r-- | target/hppa/int_helper.c | 2 | ||||
| -rw-r--r-- | target/hppa/translate.c | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7373177..9fe79b1 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -35,7 +35,7 @@ #define MMU_PHYS_IDX 4 #define TARGET_INSN_START_EXTRA_WORDS 1 -/* Hardware exceptions, interupts, faults, and traps. */ +/* Hardware exceptions, interrupts, faults, and traps. */ #define EXCP_HPMC 1 /* high priority machine check */ #define EXCP_POWER_FAIL 2 #define EXCP_RC 3 /* recovery counter */ @@ -276,7 +276,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, /* TB lookup assumes that PC contains the complete virtual address. If we leave space+offset separate, we'll get ITLB misses to an incomplete virtual address. This also means that we must separate - out current cpu priviledge from the low bits of IAOQ_F. */ + out current cpu privilege from the low bits of IAOQ_F. */ #ifdef CONFIG_USER_ONLY *pc = env->iaoq_f & -4; *cs_base = env->iaoq_b & -4; diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index d2480b1..bebc732 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -37,7 +37,7 @@ static void eval_interrupt(HPPACPU *cpu) /* Each CPU has a word mapped into the GSC bus. Anything on the GSC bus * can write to this word to raise an external interrupt on the target CPU. - * This includes the system controler (DINO) for regular devices, or + * This includes the system controller (DINO) for regular devices, or * another CPU for SMP interprocessor interrupts. */ static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d33813d..d66fcb3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1964,7 +1964,7 @@ static void do_page_zero(DisasContext *ctx) { /* If by some means we get here with PSW[N]=1, that implies that the B,GATE instruction would be skipped, and we'd fault on the - next insn within the privilaged page. */ + next insn within the privileged page. */ switch (ctx->null_cond.c) { case TCG_COND_NEVER: break; |