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author | Taylor Simpson <tsimpson@quicinc.com> | 2021-09-22 10:30:46 -0500 |
---|---|---|
committer | Taylor Simpson <tsimpson@quicinc.com> | 2021-10-06 10:29:11 -0500 |
commit | c23b5764e79f3951e98160faf6e97284453c4056 (patch) | |
tree | cb3c638ac6cf5826494103e33f4307ac8b342bc2 /target/hexagon | |
parent | e3acc2c1961cbe22ca474cd5da4163b7bbf7cea3 (diff) | |
download | qemu-c23b5764e79f3951e98160faf6e97284453c4056.zip qemu-c23b5764e79f3951e98160faf6e97284453c4056.tar.gz qemu-c23b5764e79f3951e98160faf6e97284453c4056.tar.bz2 |
Hexagon (target/hexagon) probe the stores in a packet at start of commit
When a packet has 2 stores, either both commit or neither commit.
At the beginning of gen_commit_packet, we check for multiple stores.
If there are multiple stores, call a helper that will probe each of
them before proceeding with the commit.
Note that we don't call the probe helper for packets with only one
store. Therefore, we call process_store_log before anything else
involved in committing the packet.
We also fix a typo in the comment in process_store_log.
Test case added in tests/tcg/hexagon/hex_sigsegv.c
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <1633036599-7637-1-git-send-email-tsimpson@quicinc.com>
Diffstat (limited to 'target/hexagon')
-rw-r--r-- | target/hexagon/helper.h | 2 | ||||
-rw-r--r-- | target/hexagon/op_helper.c | 16 | ||||
-rw-r--r-- | target/hexagon/translate.c | 38 |
3 files changed, 53 insertions, 3 deletions
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index ca201fb..89de2a3 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -89,3 +89,5 @@ DEF_HELPER_4(sffms_lib, f32, env, f32, f32, f32) DEF_HELPER_3(dfmpyfix, f64, env, f64, f64) DEF_HELPER_4(dfmpyhh, f64, env, f64, f64, f64) + +DEF_HELPER_2(probe_pkt_scalar_store_s0, void, env, int) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 61d5cde..af32de4 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -377,6 +377,22 @@ int32_t HELPER(vacsh_pred)(CPUHexagonState *env, return PeV; } +static void probe_store(CPUHexagonState *env, int slot, int mmu_idx) +{ + if (!(env->slot_cancelled & (1 << slot))) { + size1u_t width = env->mem_log_stores[slot].width; + target_ulong va = env->mem_log_stores[slot].va; + uintptr_t ra = GETPC(); + probe_write(env, va, width, mmu_idx, ra); + } +} + +/* Called during packet commit when there are two scalar stores */ +void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int mmu_idx) +{ + probe_store(env, 0, mmu_idx); +} + /* * mem_noshuf * Section 5.5 of the Hexagon V67 Programmer's Reference Manual diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 6fb4e68..51930e8 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -419,7 +419,7 @@ static void process_store_log(DisasContext *ctx, Packet *pkt) { /* * When a packet has two stores, the hardware processes - * slot 1 and then slot 2. This will be important when + * slot 1 and then slot 0. This will be important when * the memory accesses overlap. */ if (pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa) { @@ -471,10 +471,42 @@ static void update_exec_counters(DisasContext *ctx, Packet *pkt) static void gen_commit_packet(DisasContext *ctx, Packet *pkt) { + /* + * If there is more than one store in a packet, make sure they are all OK + * before proceeding with the rest of the packet commit. + * + * dczeroa has to be the only store operation in the packet, so we go + * ahead and process that first. + * + * When there are two scalar stores, we probe the one in slot 0. + * + * Note that we don't call the probe helper for packets with only one + * store. Therefore, we call process_store_log before anything else + * involved in committing the packet. + */ + bool has_store_s0 = pkt->pkt_has_store_s0; + bool has_store_s1 = (pkt->pkt_has_store_s1 && !ctx->s1_store_processed); + if (pkt->pkt_has_dczeroa) { + /* + * The dczeroa will be the store in slot 0, check that we don't have + * a store in slot 1. + */ + g_assert(has_store_s0 && !has_store_s1); + process_dczeroa(ctx, pkt); + } else if (has_store_s0 && has_store_s1) { + /* + * process_store_log will execute the slot 1 store first, + * so we only have to probe the store in slot 0 + */ + TCGv mem_idx = tcg_const_tl(ctx->mem_idx); + gen_helper_probe_pkt_scalar_store_s0(cpu_env, mem_idx); + tcg_temp_free(mem_idx); + } + + process_store_log(ctx, pkt); + gen_reg_writes(ctx); gen_pred_writes(ctx, pkt); - process_store_log(ctx, pkt); - process_dczeroa(ctx, pkt); update_exec_counters(ctx, pkt); if (HEX_DEBUG) { TCGv has_st0 = |