diff options
| author | Taylor Simpson <tsimpson@quicinc.com> | 2023-04-10 09:09:41 -0700 |
|---|---|---|
| committer | Taylor Simpson <tsimpson@quicinc.com> | 2023-04-21 09:32:52 -0700 |
| commit | a305a170398d80c08e19c2ef4c8637a4f4de50e1 (patch) | |
| tree | dab4ac994cd1ca8a5c528e0034d6544926ff0d97 /target/hexagon/gen_tcg.h | |
| parent | 111c529aa652fde71fe54a91776ffd166b724b42 (diff) | |
| download | qemu-a305a170398d80c08e19c2ef4c8637a4f4de50e1.zip qemu-a305a170398d80c08e19c2ef4c8637a4f4de50e1.tar.gz qemu-a305a170398d80c08e19c2ef4c8637a4f4de50e1.tar.bz2 | |
Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructions
Most of these are not modelled in QEMU, so save the overhead of
calling a helper.
The only exception is dczeroa. It assigns to hex_dczero_addr, which
is handled during packet commit.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230410202402.2856852-1-tsimpson@quicinc.com>
Diffstat (limited to 'target/hexagon/gen_tcg.h')
| -rw-r--r-- | target/hexagon/gen_tcg.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index b189f72..329e7a1 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -487,6 +487,19 @@ #define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \ fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN)) +/* dczeroa clears the 32 byte cache line at the address given */ +#define fGEN_TCG_Y2_dczeroa(SHORTCODE) SHORTCODE + +/* In linux-user mode, these are not modelled, suppress compiler warning */ +#define fGEN_TCG_Y2_dcinva(SHORTCODE) \ + do { RsV = RsV; } while (0) +#define fGEN_TCG_Y2_dccleaninva(SHORTCODE) \ + do { RsV = RsV; } while (0) +#define fGEN_TCG_Y2_dccleana(SHORTCODE) \ + do { RsV = RsV; } while (0) +#define fGEN_TCG_Y2_icinva(SHORTCODE) \ + do { RsV = RsV; } while (0) + /* * dealloc_return * Assembler mapped to @@ -1211,6 +1224,17 @@ do { \ RsV = RsV; \ } while (0) +#define fGEN_TCG_Y2_isync(SHORTCODE) \ + do { } while (0) +#define fGEN_TCG_Y2_barrier(SHORTCODE) \ + do { } while (0) +#define fGEN_TCG_Y2_syncht(SHORTCODE) \ + do { } while (0) +#define fGEN_TCG_Y2_dcfetchbo(SHORTCODE) \ + do { \ + RsV = RsV; \ + uiV = uiV; \ + } while (0) #define fGEN_TCG_J2_trap0(SHORTCODE) \ do { \ |