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| author | Taylor Simpson <ltaylorsimpson@gmail.com> | 2024-01-15 15:14:41 -0700 |
|---|---|---|
| committer | Brian Cain <bcain@quicinc.com> | 2024-01-21 22:02:33 -0800 |
| commit | 1547a2d3394d7ec87350ab8ca4022d5e0f20db01 (patch) | |
| tree | e6e271042c41bdbaa767e8c5fc4336fcf4f24aaf /target/hexagon/README | |
| parent | 7ee328804c66d93f8ab0fde35384c4f01eb7844a (diff) | |
| download | qemu-1547a2d3394d7ec87350ab8ca4022d5e0f20db01.zip qemu-1547a2d3394d7ec87350ab8ca4022d5e0f20db01.tar.gz qemu-1547a2d3394d7ec87350ab8ca4022d5e0f20db01.tar.bz2 | |
Hexagon (target/hexagon) Use QEMU decodetree (32-bit instructions)
The Decodetree Specification can be found here
https://www.qemu.org/docs/master/devel/decodetree.html
Covers all 32-bit instructions, including HVX
We generate separate decoders for each instruction class. The reason
will be more apparent in the next patch in this series.
We add 2 new scripts
gen_decodetree.py Generate the input to decodetree.py
gen_trans_funcs.py Generate the trans_* functions used by the
output of decodetree.py
Since the functions generated by decodetree.py take DisasContext * as an
argument, we add the argument to a couple of functions that didn't need
it previously. We also set the insn field in DisasContext during decode
because it is used by the trans_* functions.
There is a g_assert_not_reached() in decode_insns() in decode.c to
verify we never try to use the old decoder on 32-bit instructions
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20240115221443.365287-2-ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>
Diffstat (limited to 'target/hexagon/README')
| -rw-r--r-- | target/hexagon/README | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/target/hexagon/README b/target/hexagon/README index 69b2ffe..1b2a4d0 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -189,11 +189,16 @@ the packet, and we mark the implicit writes. After the analysis is performed, we initialize the result register for each of the predicated assignments. In addition to instruction semantics, we use a generator to create the decode -tree. This generation is also a two step process. The first step is to run -target/hexagon/gen_dectree_import.c to produce +tree. This generation is a four step process. +Step 1 is to run target/hexagon/gen_dectree_import.c to produce <BUILD_DIR>/target/hexagon/iset.py -This file is imported by target/hexagon/dectree.py to produce - <BUILD_DIR>/target/hexagon/dectree_generated.h.inc +Step 2 is to import iset.py into target/hexagon/gen_decodetree.py to produce + <BUILD_DIR>/target/hexagon/normal_decode_generated + <BUILD_DIR>/target/hexagon/hvx_decode_generated +Step 3 is to process the above files with QEMU's decodetree.py to produce + <BUILD_DIR>/target/hexagon/decode_*_generated.c.inc +Step 4 is to import iset.py into target/hexagon/gen_trans_funcs.py to produce + <BUILD_DIR>/target/hexagon/decodetree_trans_funcs_generated.c.inc *** Key Files *** |