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| author | Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> | 2022-01-06 22:00:51 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-08 15:46:10 +1000 |
| commit | fc313c64345453c7a668d765610dfd7135e21a98 (patch) | |
| tree | 336a2b0e28691f2333931bf366f85e70e60f3091 /target/arm/translate-vfp.c | |
| parent | dfdb46a3765bdab40a0b36722b4828d52ea8de96 (diff) | |
| download | qemu-fc313c64345453c7a668d765610dfd7135e21a98.zip qemu-fc313c64345453c7a668d765610dfd7135e21a98.tar.gz qemu-fc313c64345453c7a668d765610dfd7135e21a98.tar.bz2 | |
exec/memop: Adding signedness to quad definitions
Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/arm/translate-vfp.c')
| -rw-r--r-- | target/arm/translate-vfp.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 59bcaec..17f796e 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -1170,11 +1170,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) addr = add_reg_for_lit(s, a->rn, offset); tmp = tcg_temp_new_i64(); if (a->l) { - gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); + gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_UQ | MO_ALIGN_4); vfp_store_reg64(tmp, a->vd); } else { vfp_load_reg64(tmp, a->vd); - gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); + gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_UQ | MO_ALIGN_4); } tcg_temp_free_i64(tmp); tcg_temp_free_i32(addr); @@ -1322,12 +1322,12 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) for (i = 0; i < n; i++) { if (a->l) { /* load */ - gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); + gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_UQ | MO_ALIGN_4); vfp_store_reg64(tmp, a->vd + i); } else { /* store */ vfp_load_reg64(tmp, a->vd + i); - gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); + gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_UQ | MO_ALIGN_4); } tcg_gen_addi_i32(addr, addr, offset); } |