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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-05-13 09:32:37 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-05-14 15:03:08 +0100 |
| commit | e9eee5316ffec5f37643de806b2e5577c5c189cf (patch) | |
| tree | f2065386719ea249f8a0d2aed35a4ebe3fb19879 /target/arm/translate-neon.inc.c | |
| parent | 271063206a46062a45fc6bab8dabe45f0b88159d (diff) | |
| download | qemu-e9eee5316ffec5f37643de806b2e5577c5c189cf.zip qemu-e9eee5316ffec5f37643de806b2e5577c5c189cf.tar.gz qemu-e9eee5316ffec5f37643de806b2e5577c5c189cf.tar.bz2 | |
target/arm: Swap argument order for VSHL during decode
Rather than perform the argument swap during code generation,
perform it during decode. This means it doesn't have to be
special cased later, and we can share code with aarch64 code
generation. Hopefully the decode comment addresses any confusion
that might arise in between.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200513163245.17915-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-neon.inc.c')
| -rw-r--r-- | target/arm/translate-neon.inc.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index aefeff4..416302b 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -692,8 +692,7 @@ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a) uint32_t rn_ofs, uint32_t rm_ofs, \ uint32_t oprsz, uint32_t maxsz) \ { \ - /* Note the operation is vshl vd,vm,vn */ \ - tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, \ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, \ oprsz, maxsz, &OPARRAY[vece]); \ } \ DO_3SAME(INSN, gen_##INSN##_3s) |