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authorPeter Maydell <peter.maydell@linaro.org>2019-06-13 15:16:39 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-06-13 15:16:39 +0100
commit650a379d505bf558bcb41124bc6c951a76cbc113 (patch)
tree3454955dea2cf8f5cd379d906b6f82a0126e04b0 /target/arm/translate-a64.h
parent785a602eae7ad97076b9794ebaba072ad4a9f74f (diff)
parent18cf951af9a27ae573a6fa17f9d0c103f7b7679b (diff)
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190613-1' into staging
target-arm queue: * convert aarch32 VFP decoder to decodetree (includes tightening up decode in a few places) * fix minor bugs in VFP short-vector handling * hw/core/bus.c: Only the main system bus can have no parent * smmuv3: Fix decoding of ID register range * Implement NSACR gating of floating point * Use tcg_gen_gvec_bitsel # gpg: Signature made Thu 13 Jun 2019 15:15:39 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190613-1: (47 commits) target/arm: Fix short-vector increment behaviour target/arm: Convert float-to-integer VCVT insns to decodetree target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree target/arm: Convert VJCVT to decodetree target/arm: Convert integer-to-float insns to decodetree target/arm: Convert double-single precision conversion insns to decodetree target/arm: Convert VFP round insns to decodetree target/arm: Convert the VCVT-to-f16 insns to decodetree target/arm: Convert the VCVT-from-f16 insns to decodetree target/arm: Convert VFP comparison insns to decodetree target/arm: Convert VMOV (register) to decodetree target/arm: Convert VSQRT to decodetree target/arm: Convert VNEG to decodetree target/arm: Convert VABS to decodetree target/arm: Convert VMOV (imm) to decodetree target/arm: Convert VFP fused multiply-add insns to decodetree target/arm: Convert VDIV to decodetree target/arm: Convert VSUB to decodetree target/arm: Convert VADD to decodetree target/arm: Convert VNMUL to decodetree ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.h')
-rw-r--r--target/arm/translate-a64.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index 63d958c..9569bc5 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -122,5 +122,7 @@ typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
uint32_t, uint32_t);
typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t);
+typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
+ uint32_t, uint32_t, uint32_t);
#endif /* TARGET_ARM_TRANSLATE_A64_H */