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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-05-25 15:58:13 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-03 16:43:26 +0100 |
| commit | 81266a1f58bf557280c6f7ce3cad1ba8ed8a56f1 (patch) | |
| tree | e5e56230ae43c544d8d05ba36c910289ff9d1c40 /target/arm/translate-a64.c | |
| parent | 839144784b613998edf7a7277ed2ed2015b0b4d7 (diff) | |
| download | qemu-81266a1f58bf557280c6f7ce3cad1ba8ed8a56f1.zip qemu-81266a1f58bf557280c6f7ce3cad1ba8ed8a56f1.tar.gz qemu-81266a1f58bf557280c6f7ce3cad1ba8ed8a56f1.tar.bz2 | |
target/arm: Implement bfloat16 matrix multiply accumulate
This is BFMMLA for both AArch64 AdvSIMD and SVE,
and VMMLA.BF16 for AArch32 NEON.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.c')
| -rw-r--r-- | target/arm/translate-a64.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 71de75e..9ce2f5a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -12235,6 +12235,13 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) } feature = dc_isar_feature(aa64_fcma, s); break; + case 0x1d: /* BFMMLA */ + if (size != MO_16 || !is_q) { + unallocated_encoding(s); + return; + } + feature = dc_isar_feature(aa64_bf16, s); + break; case 0x1f: /* BFDOT */ switch (size) { case 1: @@ -12328,6 +12335,9 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) } return; + case 0xd: /* BFMMLA */ + gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, gen_helper_gvec_bfmmla); + return; case 0xf: /* BFDOT */ switch (size) { case 1: |