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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-09-26 13:27:00 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-09-26 13:27:01 -0700 |
| commit | d6dfd8d40cebebc3378d379cd28879e0345fbf91 (patch) | |
| tree | 30ee836e90be1f015c3fe6ceda12a388ea372ff2 /target/arm/trace-events | |
| parent | d08b8becc368cf8035eaecb49f96c135d2680615 (diff) | |
| parent | b71e2b281a23aca474e128a8487efb07e29f4019 (diff) | |
| download | qemu-master.zip qemu-master.tar.gz qemu-master.tar.bz2 | |
target-arm queue:
* reimplement VHE alias register handling
* replace magic GIC values by proper definitions
* convert power control DPRINTF() uses to trace events
* better reset related tracepoints
* implement ID_AA64PFR2_EL1
* hw/usb/hcd-uhci: don't assert for SETUP to non-0 endpoint
* net/passt: Fix build failure due to missing GIO dependency
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# gpg: Signature made Fri 26 Sep 2025 07:08:05 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [unknown]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [unknown]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [unknown]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250926' of https://gitlab.com/pm215/qemu: (44 commits)
target/arm: Implement ID_AA64PFR2_EL1
target/arm: Move ID register field defs to cpu-features.h
target/arm: Trace vCPU reset call
target/arm: Trace emulated firmware reset call
target/arm: Convert power control DPRINTF() uses to trace events
target/arm: Replace magic GIC values by proper definitions
target/arm: Remove define_arm_vh_e2h_redirects_aliases
target/arm: Rename some cpreg to their aarch64 names
target/arm: Redirect VHE FOO_EL12 to FOO_EL1 during translation
target/arm: Redirect VHE FOO_EL1 -> FOO_EL2 during translation
target/arm: Split out redirect_cpreg
target/arm: Rename TBFLAG_A64_NV2_MEM_E20 with *_E2H
target/arm: Move endianness fixup for 32-bit registers
target/arm: Move writeback of CP_ANY fields
target/arm: Move alias setting for wildcards
target/arm: Remove name argument to alloc_cpreg
target/arm: Hoist the allocation of ARMCPRegInfo
target/arm: Split out alloc_cpreg
target/arm: Add key parameter to add_cpreg_to_hashtable
target/arm: Move cpreg elimination to define_one_arm_cp_reg
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/trace-events')
| -rw-r--r-- | target/arm/trace-events | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/arm/trace-events b/target/arm/trace-events index 4438dce..72a2c7d 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -13,3 +13,13 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d" # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64 + +# cpu.c +arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 +arm_emulate_firmware_reset(uint64_t mp_aff, unsigned target_el) "cpu %" PRIu64 " @EL%u" + +# arm-powerctl.c +arm_powerctl_set_cpu_on(uint64_t mp_aff, unsigned target_el, const char *mode, uint64_t entry, uint64_t context_id) "cpu %" PRIu64 " (EL %u, %s) @ 0x%" PRIx64 " with R0 = 0x%" PRIx64 +arm_powerctl_set_cpu_on_and_reset(uint64_t mp_aff) "cpu %" PRIu64 +arm_powerctl_set_cpu_off(uint64_t mp_aff) "cpu %" PRIu64 +arm_powerctl_reset_cpu(uint64_t mp_aff) "cpu %" PRIu64 |