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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-02-06 13:29:20 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-02-15 14:32:38 +0000 |
| commit | fe31d6c72d0046eb633db51dc1d8fb9b231d270f (patch) | |
| tree | 268c3f957692b4a0528bda5032bd523f98e1a880 /target/arm/tcg | |
| parent | b2f24983db11dd1345db95f54a6d1dce184224a3 (diff) | |
| download | qemu-fe31d6c72d0046eb633db51dc1d8fb9b231d270f.zip qemu-fe31d6c72d0046eb633db51dc1d8fb9b231d270f.tar.gz qemu-fe31d6c72d0046eb633db51dc1d8fb9b231d270f.tar.bz2 | |
target/arm: The Cortex-R52 has a read-only CBAR
The Cortex-R52 implements the Configuration Base Address Register
(CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU
type, so that our implementation provides the register and the
associated qdev property.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/tcg')
| -rw-r--r-- | target/arm/tcg/cpu32.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 1125305..311d654 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -809,6 +809,7 @@ static void cortex_r52_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); cpu->midr = 0x411fd133; /* r1p3 */ cpu->revidr = 0x00000000; cpu->reset_fpsid = 0x41034023; |