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| author | Jinjie Ruan <ruanjinjie@huawei.com> | 2024-04-19 14:32:57 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-04-25 10:21:04 +0100 |
| commit | cbf817a2ff7dc12b62e0bccc15ae93369ea5829e (patch) | |
| tree | e38ab2c44c32c3d997c98e66d606956a26229c65 /target/arm/tcg/helper-a64.h | |
| parent | 4833c75611e334164b970c79be95f239ce676ab1 (diff) | |
| download | qemu-cbf817a2ff7dc12b62e0bccc15ae93369ea5829e.zip qemu-cbf817a2ff7dc12b62e0bccc15ae93369ea5829e.tar.gz qemu-cbf817a2ff7dc12b62e0bccc15ae93369ea5829e.tar.bz2 | |
target/arm: Implement ALLINT MSR (immediate)
Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
EL0 check is necessary to ALLINT, and the EL1 check is necessary when
imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
unconditional write to pc and use raise_exception_ra to unwind.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-5-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/tcg/helper-a64.h')
| -rw-r--r-- | target/arm/tcg/helper-a64.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h index 575a5da..0518165 100644 --- a/target/arm/tcg/helper-a64.h +++ b/target/arm/tcg/helper-a64.h @@ -22,6 +22,7 @@ DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_2(msr_i_spsel, void, env, i32) DEF_HELPER_2(msr_i_daifset, void, env, i32) DEF_HELPER_2(msr_i_daifclear, void, env, i32) +DEF_HELPER_1(msr_set_allint_el1, void, env) DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) |