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author | Alex Bennée <alex.bennee@linaro.org> | 2023-08-31 09:45:16 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2023-08-31 09:45:16 +0100 |
commit | 9e771a2fc68d98c5719b877e008d1dca64e6896e (patch) | |
tree | 45efb3c1f01ffea86d0abd2a218e0283d984854f /target/arm/tcg/cpu64.c | |
parent | df9a391757c7fc5a6c88f6d32b82d6f2f860bd1d (diff) | |
download | qemu-9e771a2fc68d98c5719b877e008d1dca64e6896e.zip qemu-9e771a2fc68d98c5719b877e008d1dca64e6896e.tar.gz qemu-9e771a2fc68d98c5719b877e008d1dca64e6896e.tar.bz2 |
target/arm: properly document FEAT_CRC32
This is a mandatory feature for Armv8.1 architectures but we don't
state the feature clearly in our emulation list. Also include
FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
Cc: qemu-stable@nongnu.org
Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
[PMM: pluralize 'instructions' in docs]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/tcg/cpu64.c')
-rw-r--r-- | target/arm/tcg/cpu64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 11e406d..0f89729 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -788,7 +788,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ - t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); + t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */ t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ |