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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-07-08 20:45:25 +0530 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-07-11 13:43:51 +0100 |
| commit | 6b5a3bdf3a71ab3f3bc1e9665ea54ca47c0455ec (patch) | |
| tree | 934a42b7fdc61bdf25a015a99f10759d599a3741 /target/arm/sve.decode | |
| parent | 7dbfafc157290b52af6109b82b8398d10ef5c3b3 (diff) | |
| download | qemu-6b5a3bdf3a71ab3f3bc1e9665ea54ca47c0455ec.zip qemu-6b5a3bdf3a71ab3f3bc1e9665ea54ca47c0455ec.tar.gz qemu-6b5a3bdf3a71ab3f3bc1e9665ea54ca47c0455ec.tar.bz2 | |
target/arm: Implement SCLAMP, UCLAMP
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve.decode')
| -rw-r--r-- | target/arm/sve.decode | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a9e48f0..14b3a69 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1695,3 +1695,8 @@ PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ @psel esz=2 imm=%psel_imm_s PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ @psel esz=3 imm=%psel_imm_d + +### SVE clamp + +SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm +UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm |