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| author | Anton Johansson <anjo@rev.ng> | 2023-09-12 17:34:18 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-10-03 08:01:02 -0700 |
| commit | a81fef4b6440046e21e3531329e1e21f58645c76 (patch) | |
| tree | 3f53235a814c5a382ffb620e168ece4ed3eb2f77 /target/arm/ptw.c | |
| parent | 23af78b070ebfc0bfa8f114796a2eb9b5ed31e92 (diff) | |
| download | qemu-a81fef4b6440046e21e3531329e1e21f58645c76.zip qemu-a81fef4b6440046e21e3531329e1e21f58645c76.tar.gz qemu-a81fef4b6440046e21e3531329e1e21f58645c76.tar.bz2 | |
target/arm: Replace TARGET_PAGE_ENTRY_EXTRA
TARGET_PAGE_ENTRY_EXTRA is a macro that allows guests to specify additional
fields for caching with the full TLB entry. This macro is replaced with
a union in CPUTLBEntryFull, thus making CPUTLB target-agnostic at the
cost of slightly inflated CPUTLBEntryFull for non-arm guests.
Note, this is needed to ensure that fields in CPUTLB don't vary in
offset between various targets.
(arm is the only guest actually making use of this feature.)
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230912153428.17816-2-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/ptw.c')
| -rw-r--r-- | target/arm/ptw.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/ptw.c b/target/arm/ptw.c index bfbab26..95db9ec 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -579,7 +579,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, } ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK); ptw->out_rw = full->prot & PAGE_WRITE; - pte_attrs = full->pte_attrs; + pte_attrs = full->extra.arm.pte_attrs; ptw->out_space = full->attrs.space; #else g_assert_not_reached(); @@ -2036,7 +2036,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - result->f.guarded = extract64(attrs, 50, 1); /* GP */ + result->f.extra.arm.guarded = extract64(attrs, 50, 1); /* GP */ } } |