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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-01-30 18:24:57 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-02-03 12:59:24 +0000 |
| commit | 34a8a07e57bba6df2c1c67cc9bd3e80706ce4a54 (patch) | |
| tree | bc565fb916896d2d55f38e0785b71cb42b91d334 /target/arm/helper.c | |
| parent | 5572f7557fdd1b5c36aee899b7e86fda66c2babf (diff) | |
| download | qemu-34a8a07e57bba6df2c1c67cc9bd3e80706ce4a54.zip qemu-34a8a07e57bba6df2c1c67cc9bd3e80706ce4a54.tar.gz qemu-34a8a07e57bba6df2c1c67cc9bd3e80706ce4a54.tar.bz2 | |
target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps.
These trap execution of the SVC instruction from AArch32 and AArch64.
(As usual, AArch32 can only trap from EL0, as fine grained traps are
disabled with an AArch32 EL1.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-22-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-22-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 6151c77..c62ed05 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11842,6 +11842,20 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } +static inline bool fgt_svc(CPUARMState *env, int el) +{ + /* + * Assuming fine-grained-traps are active, return true if we + * should be trapping on SVC instructions. Only AArch64 can + * trap on an SVC at EL1, but we don't need to special-case this + * because if this is AArch32 EL1 then arm_fgt_active() is false. + * We also know el is 0 or 1. + */ + return el == 0 ? + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) : + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); +} + static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) @@ -11927,6 +11941,9 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, if (arm_fgt_active(env, el)) { DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); + if (fgt_svc(env, el)) { + DP_TBFLAG_ANY(flags, FGT_SVC, 1); + } } if (env->uncached_cpsr & CPSR_IL) { @@ -12068,6 +12085,9 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) { DP_TBFLAG_A64(flags, FGT_ERET, 1); } + if (fgt_svc(env, el)) { + DP_TBFLAG_ANY(flags, FGT_SVC, 1); + } } if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { |