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author | Peter Maydell <peter.maydell@linaro.org> | 2022-08-19 12:00:49 +0100 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2022-09-14 11:19:40 +0100 |
commit | 32957aad8ce3cd4f923b464efb80645963479ff8 (patch) | |
tree | fc5d6fa8c35c4181a247b4a9a7467e1cf920a65e /target/arm/helper.c | |
parent | 62b6f5e2f0a029810791dde6e02f86ad8575a02c (diff) | |
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target/arm: Implement ID_MMFR5
In Armv8.6 a new AArch32 ID register ID_MMFR5 is defined.
Implement this; we want to be able to use it to report to
the guest that we implement FEAT_ETS.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220819110052.2942289-4-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
-rw-r--r-- | target/arm/helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index c171770..0737851 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7586,11 +7586,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = 0 }, - { .name = "RES_0_C0_C3_6", .state = ARM_CP_STATE_BOTH, + { .name = "ID_MMFR5", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_mmfr5 }, { .name = "RES_0_C0_C3_7", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, |