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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-02-06 23:34:55 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-02-16 16:00:47 +0000 |
| commit | 0f150c8499e970bd079a80394ccf65bcd7a54f12 (patch) | |
| tree | 54fbef9a92433e81ba5f11f2fd7bc9175535cb8a /target/arm/helper.c | |
| parent | eda349be62d2c7441d9dfd5ca62b5af4db919e41 (diff) | |
| download | qemu-0f150c8499e970bd079a80394ccf65bcd7a54f12.zip qemu-0f150c8499e970bd079a80394ccf65bcd7a54f12.tar.gz qemu-0f150c8499e970bd079a80394ccf65bcd7a54f12.tar.bz2 | |
target/arm: Constify ID_PFR1 on user emulation
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230206223502.25122-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index c62ed05..22670c2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7021,6 +7021,7 @@ static void define_pmu_regs(ARMCPU *cpu) } } +#ifndef CONFIG_USER_ONLY /* * We don't know until after realize whether there's a GICv3 * attached, and that is what registers the gicv3 sysregs. @@ -7038,7 +7039,6 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) return pfr1; } -#ifndef CONFIG_USER_ONLY static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = env_archcpu(env); @@ -7998,8 +7998,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, .access = PL1_R, .type = ARM_CP_NO_RAW, .accessfn = access_aa32_tid3, +#ifdef CONFIG_USER_ONLY + .type = ARM_CP_CONST, + .resetvalue = cpu->isar.id_pfr1, +#else + .type = ARM_CP_NO_RAW, + .accessfn = access_aa32_tid3, .readfn = id_pfr1_read, - .writefn = arm_cp_write_ignore }, + .writefn = arm_cp_write_ignore +#endif + }, { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, |