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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-06 13:02:38 -0500 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-09 11:47:54 +0100 |
| commit | 7cb1e61851332ea661d4ef6c1d958e3cdbffe2d8 (patch) | |
| tree | 6d3be2d6b99f76421abb82dd797ee31b5a47745f /target/arm/cpu64.c | |
| parent | 74b17e16695b93261b1c3ffb73031d574aba2b8e (diff) | |
| download | qemu-7cb1e61851332ea661d4ef6c1d958e3cdbffe2d8.zip qemu-7cb1e61851332ea661d4ef6c1d958e3cdbffe2d8.tar.gz qemu-7cb1e61851332ea661d4ef6c1d958e3cdbffe2d8.tar.bz2 | |
target/arm: Enable FEAT_CSV2_2 for -cpu max
There is no branch prediction in TCG, therefore there is no
need to actually include the context number into the predictor.
Therefore all we need to do is add the state for SCXTNUM_ELx.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu64.c')
| -rw-r--r-- | target/arm/cpu64.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 25fe74f..07b44a6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -748,7 +748,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr0 = t; t = cpu->isar.id_aa64pfr1; @@ -760,6 +760,7 @@ static void aarch64_max_initfn(Object *obj) * we do for EL2 with the virtualization=on property. */ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ + t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 = t; t = cpu->isar.id_aa64mmfr0; |