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author | Richard Henderson <richard.henderson@linaro.org> | 2022-10-10 20:18:50 -0700 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2022-10-20 11:27:49 +0100 |
commit | 937f2245596de9026ca8ae017ef47889523c4326 (patch) | |
tree | ce28803c3bcb9c174a0d3b2a849c5a4a0e44b197 /target/arm/cpu.h | |
parent | b8967ddf393aaf35fdbc07b4cb538a40f8b6fe37 (diff) | |
download | qemu-937f2245596de9026ca8ae017ef47889523c4326.zip qemu-937f2245596de9026ca8ae017ef47889523c4326.tar.gz qemu-937f2245596de9026ca8ae017ef47889523c4326.tar.bz2 |
target/arm: Use probe_access_full for BTI
Add a field to TARGET_PAGE_ENTRY_EXTRA to hold the guarded bit.
In is_guarded_page, use probe_access_full instead of just guessing
that the tlb entry is still present. Also handles the FIXME about
executing from device memory.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r-- | target/arm/cpu.h | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9a358c4..9df7adb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3388,19 +3388,6 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) /* Shared between translate-sve.c and sve_helper.c. */ extern const uint64_t pred_esz_masks[5]; -/* Helper for the macros below, validating the argument type. */ -static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) -{ - return x; -} - -/* - * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. - * Using these should be a bit more self-documenting than using the - * generic target bits directly. - */ -#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) - /* * AArch64 usage of the PAGE_TARGET_* bits for linux-user. * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect |