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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-01-30 18:24:57 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-02-03 12:59:24 +0000 |
| commit | 34a8a07e57bba6df2c1c67cc9bd3e80706ce4a54 (patch) | |
| tree | bc565fb916896d2d55f38e0785b71cb42b91d334 /target/arm/cpu.h | |
| parent | 5572f7557fdd1b5c36aee899b7e86fda66c2babf (diff) | |
| download | qemu-34a8a07e57bba6df2c1c67cc9bd3e80706ce4a54.zip qemu-34a8a07e57bba6df2c1c67cc9bd3e80706ce4a54.tar.gz qemu-34a8a07e57bba6df2c1c67cc9bd3e80706ce4a54.tar.bz2 | |
target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps.
These trap execution of the SVC instruction from AArch32 and AArch64.
(As usual, AArch32 can only trap from EL0, as fine grained traps are
disabled with an AArch32 EL1.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-22-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-22-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ec2a7716..7bc97fe 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3171,6 +3171,7 @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) +FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) /* * Bit usage when in AArch32 state, both A- and M-profile. |