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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-03-07 12:19:03 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-03-07 12:19:03 +0000 |
| commit | 2808d3b38a5232e263338e1b812bb1f6c2d56bcf (patch) | |
| tree | bdbed0d02bd0305e5c1645eacc0f6fcd7d002ac0 /target/arm/cpu.h | |
| parent | 485eb324e352a53bdf99f90511bd546eebab68f5 (diff) | |
| download | qemu-2808d3b38a5232e263338e1b812bb1f6c2d56bcf.zip qemu-2808d3b38a5232e263338e1b812bb1f6c2d56bcf.tar.gz qemu-2808d3b38a5232e263338e1b812bb1f6c2d56bcf.tar.bz2 | |
target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is
implemented. This is similar to the existing CNTVOFF_EL2, except
that it controls a hypervisor-adjustable offset made to the physical
counter and timer.
Implement the handling for this register, which includes control/trap
bits in SCR_EL3 and CNTHCTL_EL2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c827daa..bc0c848 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -452,6 +452,7 @@ typedef struct CPUArchState { uint64_t c14_cntkctl; /* Timer Control register */ uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ uint64_t cntvoff_el2; /* Counter Virtual Offset register */ + uint64_t cntpoff_el2; /* Counter Physical Offset register */ ARMGenericTimer c14_timer[NUM_GTIMERS]; uint32_t c15_cpar; /* XScale Coprocessor Access Register */ uint32_t c15_ticonfig; /* TI925T configuration byte. */ |