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authorPeter Maydell <peter.maydell@linaro.org>2017-09-07 13:54:52 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-09-07 13:54:52 +0100
commit1e577cc7cffd3de14dbd321de5c3ef191c6ab07f (patch)
tree7458a34012b0601998c8b38e7dcc4bdd396083d2 /target/arm/cpu.h
parent504e3cc36b68b34c176f3f4116b1d5677471ec20 (diff)
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target/arm: Add state field, feature bit and migration for v8M secure state
As the first step in implementing ARM v8M's security extension: * add a new feature bit ARM_FEATURE_M_SECURITY * add the CPU state field that indicates whether the CPU is currently in the secure state * add a migration subsection for this new state (we will add the Secure copies of banked register state to this subsection in later patches) * add a #define for the one new-in-v8M exception type * make the CPU debug log print S/NS status Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-4-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9fd5de7..02919a3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -66,6 +66,7 @@
#define ARMV7M_EXCP_MEM 4
#define ARMV7M_EXCP_BUS 5
#define ARMV7M_EXCP_USAGE 6
+#define ARMV7M_EXCP_SECURE 7
#define ARMV7M_EXCP_SVC 11
#define ARMV7M_EXCP_DEBUG 12
#define ARMV7M_EXCP_PENDSV 14
@@ -420,6 +421,7 @@ typedef struct CPUARMState {
int exception;
uint32_t primask;
uint32_t faultmask;
+ uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
} v7m;
/* Information associated with an exception about to be taken:
@@ -1263,6 +1265,7 @@ enum arm_features {
ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
ARM_FEATURE_PMU, /* has PMU support */
ARM_FEATURE_VBAR, /* has cp15 VBAR */
+ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
};
static inline int arm_feature(CPUARMState *env, int feature)