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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-09-12 15:04:30 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-09-21 16:07:14 +0100 |
| commit | 179e9a3baccc3918846c9fc3de2fd534a9a2f901 (patch) | |
| tree | eee711a687ac4e0d0a92eb5bf574c125e03a3759 /target/arm/cpu.h | |
| parent | 0e92818887deef2300255300af57bb58a6af1ad4 (diff) | |
| download | qemu-179e9a3baccc3918846c9fc3de2fd534a9a2f901.zip qemu-179e9a3baccc3918846c9fc3de2fd534a9a2f901.tar.gz qemu-179e9a3baccc3918846c9fc3de2fd534a9a2f901.tar.bz2 | |
target/arm: Define new TB flag for ATA0
Currently the only tag-setting instructions always do so in the
context of the current EL, and so we only need one ATA bit in the TB
flags. The FEAT_MOPS SETG instructions include ones which set tags
for a non-privileged access, so we now also need the equivalent "are
tags enabled?" information for EL0.
Add the new TB flag, and convert the existing 'bool ata' field in
DisasContext to a 'bool ata[2]' that can be indexed by the is_unpriv
bit in an instruction, similarly to mte[2].
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230912140434.1333369-9-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 266c1a9..bd55c5d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3171,6 +3171,7 @@ FIELD(TBFLAG_A64, SVL, 24, 4) FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) FIELD(TBFLAG_A64, FGT_ERET, 29, 1) FIELD(TBFLAG_A64, NAA, 30, 1) +FIELD(TBFLAG_A64, ATA0, 31, 1) /* * Helpers for using the above. |