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| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2022-03-16 17:46:41 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-03-18 11:19:19 +0000 |
| commit | 4a7319b750d2a465c9697fb0c72584c5d4e9073a (patch) | |
| tree | ce11757a63cdccb46d2ba8f99e59b4a64dc8d887 /target/arm/cpu.h | |
| parent | c28d4b8656c836b5b166b35e4c48ff26d9405b59 (diff) | |
| download | qemu-4a7319b750d2a465c9697fb0c72584c5d4e9073a.zip qemu-4a7319b750d2a465c9697fb0c72584c5d4e9073a.tar.gz qemu-4a7319b750d2a465c9697fb0c72584c5d4e9073a.tar.bz2 | |
target/arm: Make rvbar settable after realize
Make the rvbar property settable after realize. This is done
in preparation to model the ZynqMP's runtime configurable rvbar.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20220316164645.2303510-3-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 157f214..23879de 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -447,6 +447,7 @@ typedef struct CPUArchState { uint64_t vbar_el[4]; }; uint32_t mvbar; /* (monitor) vector base address register */ + uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ struct { /* FCSE PID. */ uint32_t fcseidr_ns; uint32_t fcseidr_s; @@ -985,7 +986,7 @@ struct ArchCPU { /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ uint32_t dcz_blocksize; - uint64_t rvbar; + uint64_t rvbar_prop; /* Property/input signals. */ /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ int gic_num_lrs; /* number of list registers */ |