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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-04-19 13:22:36 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-04-30 11:16:50 +0100 |
| commit | 4479ec30c9c4d2399b6e5bf4e77d136cfd27aebd (patch) | |
| tree | f4c8888291f69d3bbeeb17887498b85ab56dcf28 /target/arm/cpu.h | |
| parent | eee81d41ec4c5bf9bbde4e4d35648e29e2244f3f (diff) | |
| download | qemu-4479ec30c9c4d2399b6e5bf4e77d136cfd27aebd.zip qemu-4479ec30c9c4d2399b6e5bf4e77d136cfd27aebd.tar.gz qemu-4479ec30c9c4d2399b6e5bf4e77d136cfd27aebd.tar.bz2 | |
target/arm: Add ALIGN_MEM to TBFLAG_ANY
Use this to signal when memory access alignment is required.
This value comes from the CCR register for M-profile, and
from the SCTLR register for A-profile.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5e0131b..616b393 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3414,6 +3414,8 @@ FIELD(TBFLAG_ANY, MMUIDX, 4, 4) FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) /* For A-profile only, target EL for debug exceptions. */ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) +/* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ +FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) /* * Bit usage when in AArch32 state, both A- and M-profile. |