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author | Evgeny Iakovlev <eiakovlev@linux.microsoft.com> | 2023-01-23 17:23:03 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2023-02-03 12:59:22 +0000 |
commit | 23dcbfc080eb8a8e8395d753f07adbb0ab761143 (patch) | |
tree | 5e821f12780adcc31902a9da95eecb391a1a9771 /target/arm/cpu.c | |
parent | 3b7a165e8c94b1f7eee326fa6b68eb45f0324ea1 (diff) | |
download | qemu-23dcbfc080eb8a8e8395d753f07adbb0ab761143.zip qemu-23dcbfc080eb8a8e8395d753f07adbb0ab761143.tar.gz qemu-23dcbfc080eb8a8e8395d753f07adbb0ab761143.tar.bz2 |
hw/char/pl011: better handling of FIFO flags on LCR reset
Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual guest-visible flag update will happen
only on next data read or write attempt. As a result of that any guest
that expects RXFE flag to be set (and RXFF to be cleared) after resetting
FIFO will never see that happen.
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.c')
0 files changed, 0 insertions, 0 deletions