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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-10-13 15:12:35 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-11-07 12:13:27 +0100 |
| commit | f6524ddf86bc4af87ddc21b71151399cb47d484a (patch) | |
| tree | 633a3be6df0e8a09ab4a24fb46f0a90dd5b76fa6 /target/arm/cpu-qom.h | |
| parent | 336588a29d27d7099155b0e9fa67560f1c454f3d (diff) | |
| download | qemu-f6524ddf86bc4af87ddc21b71151399cb47d484a.zip qemu-f6524ddf86bc4af87ddc21b71151399cb47d484a.tar.gz qemu-f6524ddf86bc4af87ddc21b71151399cb47d484a.tar.bz2 | |
target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h'
These definitions and declarations are only used by
target/arm/, no need to expose them to generic hw/.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-4-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <c48c9829-3dfa-79cf-3042-454fda0d00dc@linaro.org>
Diffstat (limited to 'target/arm/cpu-qom.h')
| -rw-r--r-- | target/arm/cpu-qom.h | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index dfb9d5b..35c3b09 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -35,9 +35,6 @@ typedef struct ARMCPUInfo { void (*class_init)(ObjectClass *oc, void *data); } ARMCPUInfo; -void arm_cpu_register(const ARMCPUInfo *info); -void aarch64_cpu_register(const ARMCPUInfo *info); - /** * ARMCPUClass: * @parent_realize: The parent class' realize handler. @@ -63,29 +60,4 @@ struct AArch64CPUClass { ARMCPUClass parent_class; }; -void register_cp_regs_for_features(ARMCPU *cpu); -void init_cpreg_list(ARMCPU *cpu); - -/* Callback functions for the generic timer's timers. */ -void arm_gt_ptimer_cb(void *opaque); -void arm_gt_vtimer_cb(void *opaque); -void arm_gt_htimer_cb(void *opaque); -void arm_gt_stimer_cb(void *opaque); -void arm_gt_hvtimer_cb(void *opaque); - -#define ARM_AFF0_SHIFT 0 -#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) -#define ARM_AFF1_SHIFT 8 -#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) -#define ARM_AFF2_SHIFT 16 -#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) -#define ARM_AFF3_SHIFT 32 -#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) -#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 - -#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) -#define ARM64_AFFINITY_MASK \ - (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) -#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) - #endif |