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| author | Anton Johansson <anjo@rev.ng> | 2023-09-12 17:34:18 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-10-03 08:01:02 -0700 |
| commit | a81fef4b6440046e21e3531329e1e21f58645c76 (patch) | |
| tree | 3f53235a814c5a382ffb620e168ece4ed3eb2f77 /target/arm/cpu-param.h | |
| parent | 23af78b070ebfc0bfa8f114796a2eb9b5ed31e92 (diff) | |
| download | qemu-a81fef4b6440046e21e3531329e1e21f58645c76.zip qemu-a81fef4b6440046e21e3531329e1e21f58645c76.tar.gz qemu-a81fef4b6440046e21e3531329e1e21f58645c76.tar.bz2 | |
target/arm: Replace TARGET_PAGE_ENTRY_EXTRA
TARGET_PAGE_ENTRY_EXTRA is a macro that allows guests to specify additional
fields for caching with the full TLB entry. This macro is replaced with
a union in CPUTLBEntryFull, thus making CPUTLB target-agnostic at the
cost of slightly inflated CPUTLBEntryFull for non-arm guests.
Note, this is needed to ensure that fields in CPUTLB don't vary in
offset between various targets.
(arm is the only guest actually making use of this feature.)
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230912153428.17816-2-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/cpu-param.h')
| -rw-r--r-- | target/arm/cpu-param.h | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index b3b35f7..f9b462a 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -31,18 +31,6 @@ # define TARGET_PAGE_BITS_VARY # define TARGET_PAGE_BITS_MIN 10 -/* - * Cache the attrs and shareability fields from the page table entry. - * - * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. - * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. - * For shareability and guarded, as in the SH and GP fields respectively - * of the VMSAv8-64 PTEs. - */ -# define TARGET_PAGE_ENTRY_EXTRA \ - uint8_t pte_attrs; \ - uint8_t shareability; \ - bool guarded; #endif #endif |