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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-01-09 14:43:44 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-01-09 14:43:44 +0000 |
| commit | 67e55c73c3488762eb732f9e33f352f39093f831 (patch) | |
| tree | 094fc2fd12458a3d3497cb2e67118493d9420770 /target/arm/cpu-features.h | |
| parent | 82a65e3188abebb509510b391726711606aca642 (diff) | |
| download | qemu-67e55c73c3488762eb732f9e33f352f39093f831.zip qemu-67e55c73c3488762eb732f9e33f352f39093f831.tar.gz qemu-67e55c73c3488762eb732f9e33f352f39093f831.tar.bz2 | |
target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV
FEAT_NV defines three new bits in HCR_EL2: NV, NV1 and AT. When the
feature is enabled, allow these bits to be written, and flush the
TLBs for the bits which affect page table interpretation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>
Diffstat (limited to 'target/arm/cpu-features.h')
| -rw-r--r-- | target/arm/cpu-features.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 954d358..3a43c32 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -839,6 +839,11 @@ static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; } +static inline bool isar_feature_aa64_nv(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) != 0; +} + static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && |