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| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-12-05 07:15:21 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-12-08 18:48:26 +0000 |
| commit | 4e41d2f5830a76d3fe92b3d3b18cc9f2ee927770 (patch) | |
| tree | 60e3cc172d4aa177b460d5e72b176a8bd3c95915 /target-xtensa/cpu.c | |
| parent | fcc803d119a4c01a9b0ee5bda35fda1eeabffa33 (diff) | |
| download | qemu-4e41d2f5830a76d3fe92b3d3b18cc9f2ee927770.zip qemu-4e41d2f5830a76d3fe92b3d3b18cc9f2ee927770.tar.gz qemu-4e41d2f5830a76d3fe92b3d3b18cc9f2ee927770.tar.bz2 | |
target-xtensa: implement CACHEATTR SR
In XEA1, the Options for Memory Protection and Translation and the
corresponding TLB management instructions are not available. Instead,
functionality similar to the Region Protection Option is available
through the cache attribute register. See ISA, A.2.14 for details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/cpu.c')
| -rw-r--r-- | target-xtensa/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index c6aa45e..035b07c 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -48,6 +48,7 @@ static void xtensa_cpu_reset(CPUState *s) XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; env->sregs[VECBASE] = env->config->vecbase; env->sregs[IBREAKENABLE] = 0; + env->sregs[CACHEATTR] = 0x22222222; env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; |