From 4e41d2f5830a76d3fe92b3d3b18cc9f2ee927770 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Wed, 5 Dec 2012 07:15:21 +0400 Subject: target-xtensa: implement CACHEATTR SR In XEA1, the Options for Memory Protection and Translation and the corresponding TLB management instructions are not available. Instead, functionality similar to the Region Protection Option is available through the cache attribute register. See ISA, A.2.14 for details. Signed-off-by: Max Filippov Signed-off-by: Blue Swirl --- target-xtensa/cpu.c | 1 + 1 file changed, 1 insertion(+) (limited to 'target-xtensa/cpu.c') diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index c6aa45e..035b07c 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -48,6 +48,7 @@ static void xtensa_cpu_reset(CPUState *s) XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; env->sregs[VECBASE] = env->config->vecbase; env->sregs[IBREAKENABLE] = 0; + env->sregs[CACHEATTR] = 0x22222222; env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; -- cgit v1.1