Use dynamical computation for condition codes

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

5 files changed, 196 insertions, 24 deletions

diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 8b84789..32b45f94 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -92,6 +92,27 @@
 #define PSR_ET    (1<<5)
 #define PSR_CWP   0x1f
 
+#define CC_SRC (env->cc_src)
+#define CC_SRC2 (env->cc_src2)
+#define CC_DST (env->cc_dst)
+#define CC_OP  (env->cc_op)
+
+enum {
+    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
+    CC_OP_FLAGS,   /* all cc are back in status register */
+    CC_OP_DIV,     /* modify N, Z and V, C = 0*/
+    CC_OP_ADD,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
+    CC_OP_ADDX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
+    CC_OP_TADD,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
+    CC_OP_TADDTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
+    CC_OP_SUB,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
+    CC_OP_SUBX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
+    CC_OP_TSUB,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
+    CC_OP_TSUBTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
+    CC_OP_LOGIC,   /* modify N and Z, C = V = 0, CC_DST = res */
+    CC_OP_NB,
+};
+
 /* Trap base register */
 #define TBR_BASE_MASK 0xfffff000
 
@@ -261,6 +282,7 @@ typedef struct CPUSPARCState {
     /* emulator internal flags handling */
     target_ulong cc_src, cc_src2;
     target_ulong cc_dst;
+    uint32_t cc_op;
 
     target_ulong t0, t1; /* temporaries live across basic blocks */
     target_ulong cond; /* conditional branch result (XXX: save it in a
@@ -413,6 +435,7 @@ static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
         env->psrps = (_tmp & PSR_PS)? 1 : 0;                            \
         env->psret = (_tmp & PSR_ET)? 1 : 0;                            \
         cpu_set_cwp(env, _tmp & PSR_CWP);                               \
+        CC_OP = CC_OP_FLAGS;                                            \
     } while (0)
 
 #ifdef TARGET_SPARC64
@@ -420,6 +443,7 @@ static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
 #define PUT_CCR(env, val) do { int _tmp = val;                          \
         env->xcc = (_tmp >> 4) << 20;                                   \
         env->psr = (_tmp & 0xf) << 20;                                  \
+        CC_OP = CC_OP_FLAGS;                                            \
     } while (0)
 #define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
 
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 2ecafd1..8ad82a9 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -660,6 +660,7 @@ void cpu_reset(CPUSPARCState *env)
     env->psret = 0;
     env->psrs = 1;
     env->psrps = 1;
+    CC_OP = CC_OP_FLAGS;
 #ifdef TARGET_SPARC64
     env->pstate = PS_PRIV;
     env->hpstate = HS_PRIV;
diff --git a/target-sparc/helper.h b/target-sparc/helper.h
index 430ed2b..4002b9e 100644
--- a/target-sparc/helper.h
+++ b/target-sparc/helper.h
@@ -156,5 +156,7 @@ VIS_CMPHELPER(cmpne);
 #undef F_HELPER_DQ_0_0
 #undef VIS_HELPER
 #undef VIS_CMPHELPER
+DEF_HELPER_0(compute_psr, void);
+DEF_HELPER_0(compute_C_icc, i32);
 
 #include "def-helper.h"
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 5f86b33..2a71795 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -746,6 +746,67 @@ GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
 GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
 GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
 
+static uint32_t compute_all_flags(void)
+{
+    return env->psr & PSR_ICC;
+}
+
+static uint32_t compute_C_flags(void)
+{
+    return env->psr & PSR_CARRY;
+}
+
+#ifdef TARGET_SPARC64
+static uint32_t compute_all_flags_xcc(void)
+{
+    return env->xcc & PSR_ICC;
+}
+
+static uint32_t compute_C_flags_xcc(void)
+{
+    return env->xcc & PSR_CARRY;
+}
+
+#endif
+
+typedef struct CCTable {
+    uint32_t (*compute_all)(void); /* return all the flags */
+    uint32_t (*compute_c)(void);  /* return the C flag */
+} CCTable;
+
+static const CCTable icc_table[CC_OP_NB] = {
+    /* CC_OP_DYNAMIC should never happen */
+    [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags },
+};
+
+#ifdef TARGET_SPARC64
+static const CCTable xcc_table[CC_OP_NB] = {
+    /* CC_OP_DYNAMIC should never happen */
+    [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc },
+};
+#endif
+
+void helper_compute_psr(void)
+{
+    uint32_t new_psr;
+
+    new_psr = icc_table[CC_OP].compute_all();
+    env->psr = new_psr;
+#ifdef TARGET_SPARC64
+    new_psr = xcc_table[CC_OP].compute_all();
+    env->xcc = new_psr;
+#endif
+    CC_OP = CC_OP_FLAGS;
+}
+
+uint32_t helper_compute_C_icc(void)
+{
+    uint32_t ret;
+
+    ret = icc_table[CC_OP].compute_c() >> PSR_CARRY_SHIFT;
+    return ret;
+}
+
 #ifdef TARGET_SPARC64
 GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index ae93614..161375f 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -42,7 +42,7 @@
 
 /* global register indexes */
 static TCGv_ptr cpu_env, cpu_regwptr;
-static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
+static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst, cpu_cc_op;
 static TCGv_i32 cpu_psr;
 static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
 static TCGv cpu_y;
@@ -76,6 +76,7 @@ typedef struct DisasContext {
     int mem_idx;
     int fpu_enabled;
     int address_mask_32bit;
+    uint32_t cc_op;  /* current CC operation */
     struct TranslationBlock *tb;
     sparc_def_t *def;
 } DisasContext;
@@ -1286,7 +1287,8 @@ static inline void gen_op_next_insn(void)
     tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
 }
 
-static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
+static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
+                            DisasContext *dc)
 {
     TCGv_i32 r_src;
 
@@ -1298,6 +1300,14 @@ static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
 #else
     r_src = cpu_psr;
 #endif
+    switch (dc->cc_op) {
+    case CC_OP_FLAGS:
+        break;
+    default:
+        gen_helper_compute_psr();
+        dc->cc_op = CC_OP_FLAGS;
+        break;
+    }
     switch (cond) {
     case 0x0:
         gen_op_eval_bn(r_dst);
@@ -1474,7 +1484,7 @@ static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
         }
     } else {
         flush_cond(dc, r_cond);
-        gen_cond(r_cond, cc, cond);
+        gen_cond(r_cond, cc, cond, dc);
         if (a) {
             gen_branch_a(dc, target, dc->npc, r_cond);
             dc->is_br = 1;
@@ -2154,14 +2164,14 @@ static void disas_sparc_insn(DisasContext * dc)
 
                     save_state(dc, cpu_cond);
                     if (cc == 0)
-                        gen_cond(r_cond, 0, cond);
+                        gen_cond(r_cond, 0, cond, dc);
                     else if (cc == 2)
-                        gen_cond(r_cond, 1, cond);
+                        gen_cond(r_cond, 1, cond, dc);
                     else
                         goto illegal_insn;
 #else
                     save_state(dc, cpu_cond);
-                    gen_cond(r_cond, 0, cond);
+                    gen_cond(r_cond, 0, cond, dc);
 #endif
                     l1 = gen_new_label();
                     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
@@ -2200,6 +2210,7 @@ static void disas_sparc_insn(DisasContext * dc)
                     break;
 #ifdef TARGET_SPARC64
                 case 0x2: /* V9 rdccr */
+                    gen_helper_compute_psr();
                     gen_helper_rdccr(cpu_dst);
                     gen_movl_TN_reg(rd, cpu_dst);
                     break;
@@ -2275,6 +2286,8 @@ static void disas_sparc_insn(DisasContext * dc)
 #ifndef TARGET_SPARC64
                 if (!supervisor(dc))
                     goto priv_insn;
+                gen_helper_compute_psr();
+                dc->cc_op = CC_OP_FLAGS;
                 gen_helper_rdpsr(cpu_dst);
 #else
                 CHECK_IU_FEATURE(dc, HYPV);
@@ -2923,7 +2936,7 @@ static void disas_sparc_insn(DisasContext * dc)
                         l1 = gen_new_label();                           \
                         r_cond = tcg_temp_new();                        \
                         cond = GET_FIELD_SP(insn, 14, 17);              \
-                        gen_cond(r_cond, icc, cond);                    \
+                        gen_cond(r_cond, icc, cond, dc);                \
                         tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
                                            0, l1);                      \
                         tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);     \
@@ -2938,7 +2951,7 @@ static void disas_sparc_insn(DisasContext * dc)
                         l1 = gen_new_label();                           \
                         r_cond = tcg_temp_new();                        \
                         cond = GET_FIELD_SP(insn, 14, 17);              \
-                        gen_cond(r_cond, icc, cond);                    \
+                        gen_cond(r_cond, icc, cond, dc);                \
                         tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
                                            0, l1);                      \
                         tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)],            \
@@ -2956,7 +2969,7 @@ static void disas_sparc_insn(DisasContext * dc)
                         l1 = gen_new_label();                           \
                         r_cond = tcg_temp_new();                        \
                         cond = GET_FIELD_SP(insn, 14, 17);              \
-                        gen_cond(r_cond, icc, cond);                    \
+                        gen_cond(r_cond, icc, cond, dc);                \
                         tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
                                            0, l1);                      \
                         tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)],            \
@@ -3140,12 +3153,16 @@ static void disas_sparc_insn(DisasContext * dc)
                             simm = GET_FIELDs(insn, 19, 31);
                             if (xop & 0x10) {
                                 gen_op_addi_cc(cpu_dst, cpu_src1, simm);
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                                dc->cc_op = CC_OP_FLAGS;
                             } else {
                                 tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
                             }
                         } else {
                             if (xop & 0x10) {
                                 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                                dc->cc_op = CC_OP_FLAGS;
                             } else {
                                 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
                             }
@@ -3160,6 +3177,8 @@ static void disas_sparc_insn(DisasContext * dc)
                         }
                         if (xop & 0x10) {
                             gen_op_logic_cc(cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                            dc->cc_op = CC_OP_FLAGS;
                         }
                         break;
                     case 0x2: /* or */
@@ -3169,8 +3188,11 @@ static void disas_sparc_insn(DisasContext * dc)
                         } else {
                             tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
                         }
-                        if (xop & 0x10)
+                        if (xop & 0x10) {
                             gen_op_logic_cc(cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                            dc->cc_op = CC_OP_FLAGS;
+                        }
                         break;
                     case 0x3: /* xor */
                         if (IS_IMM) {
@@ -3179,20 +3201,27 @@ static void disas_sparc_insn(DisasContext * dc)
                         } else {
                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
                         }
-                        if (xop & 0x10)
+                        if (xop & 0x10) {
                             gen_op_logic_cc(cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                            dc->cc_op = CC_OP_FLAGS;
+                        }
                         break;
                     case 0x4: /* sub */
                         if (IS_IMM) {
                             simm = GET_FIELDs(insn, 19, 31);
                             if (xop & 0x10) {
                                 gen_op_subi_cc(cpu_dst, cpu_src1, simm);
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                                dc->cc_op = CC_OP_FLAGS;
                             } else {
                                 tcg_gen_subi_tl(cpu_dst, cpu_src1, simm);
                             }
                         } else {
                             if (xop & 0x10) {
                                 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                                dc->cc_op = CC_OP_FLAGS;
                             } else {
                                 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
                             }
@@ -3205,8 +3234,11 @@ static void disas_sparc_insn(DisasContext * dc)
                         } else {
                             tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
                         }
-                        if (xop & 0x10)
+                        if (xop & 0x10) {
                             gen_op_logic_cc(cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                            dc->cc_op = CC_OP_FLAGS;
+                        }
                         break;
                     case 0x6: /* orn */
                         if (IS_IMM) {
@@ -3215,8 +3247,11 @@ static void disas_sparc_insn(DisasContext * dc)
                         } else {
                             tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
                         }
-                        if (xop & 0x10)
+                        if (xop & 0x10) {
                             gen_op_logic_cc(cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                            dc->cc_op = CC_OP_FLAGS;
+                        }
                         break;
                     case 0x7: /* xorn */
                         if (IS_IMM) {
@@ -3226,23 +3261,34 @@ static void disas_sparc_insn(DisasContext * dc)
                             tcg_gen_not_tl(cpu_tmp0, cpu_src2);
                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
                         }
-                        if (xop & 0x10)
+                        if (xop & 0x10) {
                             gen_op_logic_cc(cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                            dc->cc_op = CC_OP_FLAGS;
+                        }
                         break;
                     case 0x8: /* addx, V9 addc */
                         if (IS_IMM) {
                             simm = GET_FIELDs(insn, 19, 31);
-                            if (xop & 0x10)
+                            if (xop & 0x10) {
+                                gen_helper_compute_psr();
                                 gen_op_addxi_cc(cpu_dst, cpu_src1, simm);
-                            else {
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                                dc->cc_op = CC_OP_FLAGS;
+                            } else {
+                                gen_helper_compute_psr();
                                 gen_mov_reg_C(cpu_tmp0, cpu_psr);
                                 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm);
                                 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
                             }
                         } else {
-                            if (xop & 0x10)
+                            if (xop & 0x10) {
+                                gen_helper_compute_psr();
                                 gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
-                            else {
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                                dc->cc_op = CC_OP_FLAGS;
+                            } else {
+                                gen_helper_compute_psr();
                                 gen_mov_reg_C(cpu_tmp0, cpu_psr);
                                 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
                                 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
@@ -3262,29 +3308,43 @@ static void disas_sparc_insn(DisasContext * dc)
                     case 0xa: /* umul */
                         CHECK_IU_FEATURE(dc, MUL);
                         gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
-                        if (xop & 0x10)
+                        if (xop & 0x10) {
                             gen_op_logic_cc(cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                            dc->cc_op = CC_OP_FLAGS;
+                        }
                         break;
                     case 0xb: /* smul */
                         CHECK_IU_FEATURE(dc, MUL);
                         gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
-                        if (xop & 0x10)
+                        if (xop & 0x10) {
                             gen_op_logic_cc(cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                            dc->cc_op = CC_OP_FLAGS;
+                        }
                         break;
                     case 0xc: /* subx, V9 subc */
                         if (IS_IMM) {
                             simm = GET_FIELDs(insn, 19, 31);
                             if (xop & 0x10) {
+                                gen_helper_compute_psr();
                                 gen_op_subxi_cc(cpu_dst, cpu_src1, simm);
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                                dc->cc_op = CC_OP_FLAGS;
                             } else {
+                                gen_helper_compute_psr();
                                 gen_mov_reg_C(cpu_tmp0, cpu_psr);
                                 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm);
                                 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
                             }
                         } else {
                             if (xop & 0x10) {
+                                gen_helper_compute_psr();
                                 gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                                dc->cc_op = CC_OP_FLAGS;
                             } else {
+                                gen_helper_compute_psr();
                                 gen_mov_reg_C(cpu_tmp0, cpu_psr);
                                 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
                                 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
@@ -3302,14 +3362,20 @@ static void disas_sparc_insn(DisasContext * dc)
                     case 0xe: /* udiv */
                         CHECK_IU_FEATURE(dc, DIV);
                         gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2);
-                        if (xop & 0x10)
+                        if (xop & 0x10) {
                             gen_op_div_cc(cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                            dc->cc_op = CC_OP_FLAGS;
+                        }
                         break;
                     case 0xf: /* sdiv */
                         CHECK_IU_FEATURE(dc, DIV);
                         gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2);
-                        if (xop & 0x10)
+                        if (xop & 0x10) {
                             gen_op_div_cc(cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                            dc->cc_op = CC_OP_FLAGS;
+                        }
                         break;
                     default:
                         goto illegal_insn;
@@ -3322,24 +3388,35 @@ static void disas_sparc_insn(DisasContext * dc)
                     case 0x20: /* taddcc */
                         gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
                         gen_movl_TN_reg(rd, cpu_dst);
+                        tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                        dc->cc_op = CC_OP_FLAGS;
                         break;
                     case 0x21: /* tsubcc */
                         gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
                         gen_movl_TN_reg(rd, cpu_dst);
+                        tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                        dc->cc_op = CC_OP_FLAGS;
                         break;
                     case 0x22: /* taddcctv */
                         save_state(dc, cpu_cond);
                         gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
                         gen_movl_TN_reg(rd, cpu_dst);
+                        tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                        dc->cc_op = CC_OP_FLAGS;
                         break;
                     case 0x23: /* tsubcctv */
                         save_state(dc, cpu_cond);
                         gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
                         gen_movl_TN_reg(rd, cpu_dst);
+                        tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                        dc->cc_op = CC_OP_FLAGS;
                         break;
                     case 0x24: /* mulscc */
+                        gen_helper_compute_psr();
                         gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
                         gen_movl_TN_reg(rd, cpu_dst);
+                        tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                        dc->cc_op = CC_OP_FLAGS;
                         break;
 #ifndef TARGET_SPARC64
                     case 0x25:  /* sll */
@@ -3394,6 +3471,8 @@ static void disas_sparc_insn(DisasContext * dc)
                             case 0x2: /* V9 wrccr */
                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
                                 gen_helper_wrccr(cpu_dst);
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                                dc->cc_op = CC_OP_FLAGS;
                                 break;
                             case 0x3: /* V9 wrasi */
                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
@@ -3525,6 +3604,8 @@ static void disas_sparc_insn(DisasContext * dc)
 #else
                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
                             gen_helper_wrpsr(cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+                            dc->cc_op = CC_OP_FLAGS;
                             save_state(dc, cpu_cond);
                             gen_op_next_insn();
                             tcg_gen_exit_tb(0);
@@ -3739,9 +3820,9 @@ static void disas_sparc_insn(DisasContext * dc)
                             r_cond = tcg_temp_new();
                             if (insn & (1 << 18)) {
                                 if (cc == 0)
-                                    gen_cond(r_cond, 0, cond);
+                                    gen_cond(r_cond, 0, cond, dc);
                                 else if (cc == 2)
-                                    gen_cond(r_cond, 1, cond);
+                                    gen_cond(r_cond, 1, cond, dc);
                                 else
                                     goto illegal_insn;
                             } else {
@@ -4919,6 +5000,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
     dc->pc = pc_start;
     last_pc = dc->pc;
     dc->npc = (target_ulong) tb->cs_base;
+    dc->cc_op = CC_OP_DYNAMIC;
     dc->mem_idx = cpu_mmu_index(env);
     dc->def = env->def;
     if ((dc->def->features & CPU_FEATURE_FLOAT))
@@ -5131,6 +5213,8 @@ void gen_intermediate_code_init(CPUSPARCState *env)
                                          "cc_src2");
         cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
                                         "cc_dst");
+        cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op),
+                                           "cc_op");
         cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, psr),
                                          "psr");
         cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, fsr),