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| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-03-02 18:22:19 +0000 |
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| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-03-02 18:22:19 +0000 |
| commit | 38bc628b08e5d43024cb407cd0605a068fcc5536 (patch) | |
| tree | ac8e166f6465eff8529858f5c176015a526e5496 /target-sparc | |
| parent | 0cf767d663272011b65dfc1ef4940146c6b5db20 (diff) | |
| download | qemu-38bc628b08e5d43024cb407cd0605a068fcc5536.zip qemu-38bc628b08e5d43024cb407cd0605a068fcc5536.tar.gz qemu-38bc628b08e5d43024cb407cd0605a068fcc5536.tar.bz2 | |
Convert addx, subx, next_insn and mov_pc_npc to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4009 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
| -rw-r--r-- | target-sparc/op.c | 21 | ||||
| -rw-r--r-- | target-sparc/translate.c | 35 |
2 files changed, 29 insertions, 27 deletions
diff --git a/target-sparc/op.c b/target-sparc/op.c index ee5b08c..eadd1fd 100644 --- a/target-sparc/op.c +++ b/target-sparc/op.c @@ -215,11 +215,6 @@ void OPPROTO op_add_T1_T0_cc(void) FORCE_RET(); } -void OPPROTO op_addx_T1_T0(void) -{ - T0 += T1 + FLAG_SET(PSR_CARRY); -} - void OPPROTO op_addx_T1_T0_cc(void) { target_ulong src1; @@ -413,11 +408,6 @@ void OPPROTO op_sub_T1_T0_cc(void) FORCE_RET(); } -void OPPROTO op_subx_T1_T0(void) -{ - T0 -= T1 + FLAG_SET(PSR_CARRY); -} - void OPPROTO op_subx_T1_T0_cc(void) { target_ulong src1; @@ -1184,17 +1174,6 @@ void OPPROTO op_eval_brgez(void) } #endif -void OPPROTO op_mov_pc_npc(void) -{ - env->pc = env->npc; -} - -void OPPROTO op_next_insn(void) -{ - env->pc = env->npc; - env->npc = env->npc + 4; -} - void OPPROTO op_jmp_label(void) { GOTO_LABEL_PARAM(1); diff --git a/target-sparc/translate.c b/target-sparc/translate.c index b93a087..a366b1f 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -412,16 +412,26 @@ static inline void gen_mov_pc_npc(DisasContext * dc) { if (dc->npc == JUMP_PC) { gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]); - gen_op_mov_pc_npc(); + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc)); + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc)); dc->pc = DYNAMIC_PC; } else if (dc->npc == DYNAMIC_PC) { - gen_op_mov_pc_npc(); + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc)); + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc)); dc->pc = DYNAMIC_PC; } else { dc->pc = dc->npc; } } +static inline void gen_op_next_insn(void) +{ + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc)); + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc)); + tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, 4); + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc)); +} + static GenOpFunc * const gen_cond[2][16] = { { gen_op_eval_bn, @@ -991,6 +1001,13 @@ static inline void gen_ldstub_asi(int insn) } #endif +static inline void gen_mov_reg_C(TCGv reg) +{ + tcg_gen_ld_i32(reg, cpu_env, offsetof(CPUSPARCState, psr)); + tcg_gen_shri_i32(reg, reg, 20); + tcg_gen_andi_i32(reg, reg, 0x1); +} + /* before an instruction, dc->pc must be static */ static void disas_sparc_insn(DisasContext * dc) { @@ -2111,8 +2128,11 @@ static void disas_sparc_insn(DisasContext * dc) case 0x8: if (xop & 0x10) gen_op_addx_T1_T0_cc(); - else - gen_op_addx_T1_T0(); + else { + gen_mov_reg_C(cpu_tmp0); + tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + } break; #ifdef TARGET_SPARC64 case 0x9: /* V9 mulx */ @@ -2132,8 +2152,11 @@ static void disas_sparc_insn(DisasContext * dc) case 0xc: if (xop & 0x10) gen_op_subx_T1_T0_cc(); - else - gen_op_subx_T1_T0(); + else { + gen_mov_reg_C(cpu_tmp0); + tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); + tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + } break; #ifdef TARGET_SPARC64 case 0xd: /* V9 udivx */ |