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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2015-08-17 17:34:10 +1000 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2015-09-11 08:15:28 -0700 |
| commit | 97ed5ccdee95f0b98bedc601ff979e368583472c (patch) | |
| tree | 5ee711528010f3700f13983b8222c2ca7ae85c83 /target-sparc/translate.c | |
| parent | ba9cef7b6e487a5a8969db81d09b8eec8a2b50c6 (diff) | |
| download | qemu-97ed5ccdee95f0b98bedc601ff979e368583472c.zip qemu-97ed5ccdee95f0b98bedc601ff979e368583472c.tar.gz qemu-97ed5ccdee95f0b98bedc601ff979e368583472c.tar.bz2 | |
tlb: Add "ifetch" argument to cpu_mmu_index()
This is set to true when the index is for an instruction fetch
translation.
The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS
acessors.
All targets ignore it for now, and all other callers pass "false".
This will allow targets who wish to split the mmu index between
instruction and data accesses to do so. A subsequent patch will
do just that for PowerPC.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-sparc/translate.c')
| -rw-r--r-- | target-sparc/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 48fc2ab..4690b46 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5234,7 +5234,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu, last_pc = dc->pc; dc->npc = (target_ulong) tb->cs_base; dc->cc_op = CC_OP_DYNAMIC; - dc->mem_idx = cpu_mmu_index(env); + dc->mem_idx = cpu_mmu_index(env, false); dc->def = env->def; dc->fpu_enabled = tb_fpu_enabled(tb->flags); dc->address_mask_32bit = tb_am_enabled(tb->flags); |