SH4: use TCG variables for gregs

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5102 c046a42c-6fe2-441c-8c8c-71466251a162

1 files changed, 202 insertions, 200 deletions

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 5cf2abf..be3b29e 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -57,18 +57,38 @@ enum {
     BS_EXCP     = 3, /* We reached an exception condition */
 };
 
-static TCGv cpu_env, cpu_T[2];
+/* global register indexes */
+static TCGv cpu_env;
+static TCGv cpu_gregs[24];
+
+/* dyngen register indexes */
+static TCGv cpu_T[2];
 
 #include "gen-icount.h"
 
 static void sh4_translate_init(void)
 {
+    int i;
     static int done_init = 0;
+    static const char * const gregnames[24] = { 
+        "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
+        "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
+        "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
+        "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
+        "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
+    };
+
     if (done_init)
         return;
+
     cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
-    cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
-    cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
+    cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG1, "T0");
+    cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG2, "T1");
+
+    for (i = 0; i < 24; i++)
+        cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
+                                          offsetof(CPUState, gregs[i]),
+                                          gregnames[i]);
 
     /* register helpers */
 #undef DEF_HELPER
@@ -78,24 +98,6 @@ static void sh4_translate_init(void)
     done_init = 1;
 }
 
-/* General purpose registers moves. */
-static inline void gen_movl_imm_rN(uint32_t arg, int reg)
-{
-    TCGv tmp = tcg_const_i32(arg);
-    tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, gregs[reg]));
-    tcg_temp_free(tmp);
-}
-
-static always_inline void gen_movl_T_rN (TCGv t, int reg)
-{
-    tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, gregs[reg]));
-}
-
-static always_inline void gen_movl_rN_T (TCGv t, int reg)
-{
-    tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, gregs[reg]));
-}
-
 #ifdef CONFIG_USER_ONLY
 
 #define GEN_OP_LD(width, reg) \
@@ -340,29 +342,29 @@ void _decode_opc(DisasContext * ctx)
 
     switch (ctx->opcode & 0xf000) {
     case 0x1000:		/* mov.l Rm,@(disp,Rn) */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_addl_imm_T1(B3_0 * 4);
 	gen_op_stl_T0_T1(ctx);
 	return;
     case 0x5000:		/* mov.l @(disp,Rm),Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_addl_imm_T0(B3_0 * 4);
 	gen_op_ldl_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0xe000:		/* mov #imm,Rn */
-	gen_movl_imm_rN(B7_0s, REG(B11_8));
+	tcg_gen_movi_i32(cpu_gregs[REG(B11_8)], B7_0s);
 	return;
     case 0x9000:		/* mov.w @(disp,PC),Rn */
 	tcg_gen_movi_i32(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
 	gen_op_ldw_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0xd000:		/* mov.l @(disp,PC),Rn */
 	tcg_gen_movi_i32(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
 	gen_op_ldl_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x7000:		/* add #imm,Rn */
 	gen_op_add_imm_rN(B7_0s, REG(B11_8));
@@ -382,324 +384,324 @@ void _decode_opc(DisasContext * ctx)
 
     switch (ctx->opcode & 0xf00f) {
     case 0x6003:		/* mov Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x2000:		/* mov.b Rm,@Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_stb_T0_T1(ctx);
 	return;
     case 0x2001:		/* mov.w Rm,@Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_stw_T0_T1(ctx);
 	return;
     case 0x2002:		/* mov.l Rm,@Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_stl_T0_T1(ctx);
 	return;
     case 0x6000:		/* mov.b @Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_ldb_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x6001:		/* mov.w @Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_ldw_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x6002:		/* mov.l @Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_ldl_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x2004:		/* mov.b Rm,@-Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_dec1_rN(REG(B11_8));    /* modify register status */
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_inc1_rN(REG(B11_8));    /* recover register status */
 	gen_op_stb_T0_T1(ctx);         /* might cause re-execution */
 	gen_op_dec1_rN(REG(B11_8));    /* modify register status */
 	return;
     case 0x2005:		/* mov.w Rm,@-Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_dec2_rN(REG(B11_8));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_inc2_rN(REG(B11_8));
 	gen_op_stw_T0_T1(ctx);
 	gen_op_dec2_rN(REG(B11_8));
 	return;
     case 0x2006:		/* mov.l Rm,@-Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_dec4_rN(REG(B11_8));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_inc4_rN(REG(B11_8));
 	gen_op_stl_T0_T1(ctx);
 	gen_op_dec4_rN(REG(B11_8));
 	return;
     case 0x6004:		/* mov.b @Rm+,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_ldb_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	if ( B11_8 != B7_4 )
 		gen_op_inc1_rN(REG(B7_4));
 	return;
     case 0x6005:		/* mov.w @Rm+,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_ldw_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	if ( B11_8 != B7_4 )
 		gen_op_inc2_rN(REG(B7_4));
 	return;
     case 0x6006:		/* mov.l @Rm+,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_ldl_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	if ( B11_8 != B7_4 )
 		gen_op_inc4_rN(REG(B7_4));
 	return;
     case 0x0004:		/* mov.b Rm,@(R0,Rn) */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_add_rN_T1(REG(0));
 	gen_op_stb_T0_T1(ctx);
 	return;
     case 0x0005:		/* mov.w Rm,@(R0,Rn) */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_add_rN_T1(REG(0));
 	gen_op_stw_T0_T1(ctx);
 	return;
     case 0x0006:		/* mov.l Rm,@(R0,Rn) */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_add_rN_T1(REG(0));
 	gen_op_stl_T0_T1(ctx);
 	return;
     case 0x000c:		/* mov.b @(R0,Rm),Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_add_rN_T0(REG(0));
 	gen_op_ldb_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x000d:		/* mov.w @(R0,Rm),Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_add_rN_T0(REG(0));
 	gen_op_ldw_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x000e:		/* mov.l @(R0,Rm),Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_add_rN_T0(REG(0));
 	gen_op_ldl_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x6008:		/* swap.b Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_swapb_T0();
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x6009:		/* swap.w Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_swapw_T0();
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x200d:		/* xtrct Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_xtrct_T0_T1();
-	gen_movl_T_rN(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
 	return;
     case 0x300c:		/* add Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_add_T0_rN(REG(B11_8));
 	return;
     case 0x300e:		/* addc Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_addc_T0_T1();
-	gen_movl_T_rN(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
 	return;
     case 0x300f:		/* addv Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_addv_T0_T1();
-	gen_movl_T_rN(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
 	return;
     case 0x2009:		/* and Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_and_T0_rN(REG(B11_8));
 	return;
     case 0x3000:		/* cmp/eq Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_cmp_eq_T0_T1();
 	return;
     case 0x3003:		/* cmp/ge Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_cmp_ge_T0_T1();
 	return;
     case 0x3007:		/* cmp/gt Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_cmp_gt_T0_T1();
 	return;
     case 0x3006:		/* cmp/hi Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_cmp_hi_T0_T1();
 	return;
     case 0x3002:		/* cmp/hs Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_cmp_hs_T0_T1();
 	return;
     case 0x200c:		/* cmp/str Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_cmp_str_T0_T1();
 	return;
     case 0x2007:		/* div0s Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_div0s_T0_T1();
 	return;
     case 0x3004:		/* div1 Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_div1_T0_T1();
-	gen_movl_T_rN(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
 	return;
     case 0x300d:		/* dmuls.l Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_dmulsl_T0_T1();
 	return;
     case 0x3005:		/* dmulu.l Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_dmulul_T0_T1();
 	return;
     case 0x600e:		/* exts.b Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
 	tcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x600f:		/* exts.w Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
 	tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x600c:		/* extu.b Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x600d:		/* extu.w Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x000f:		/* mac.l @Rm+,@Rn+ */
-	gen_movl_rN_T(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
 	gen_op_ldl_T0_T0(ctx);
 	tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_ldl_T0_T0(ctx);
 	gen_op_macl_T0_T1();
 	gen_op_inc4_rN(REG(B11_8));
 	gen_op_inc4_rN(REG(B7_4));
 	return;
     case 0x400f:		/* mac.w @Rm+,@Rn+ */
-	gen_movl_rN_T(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
 	gen_op_ldl_T0_T0(ctx);
 	tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_ldl_T0_T0(ctx);
 	gen_op_macw_T0_T1();
 	gen_op_inc2_rN(REG(B11_8));
 	gen_op_inc2_rN(REG(B7_4));
 	return;
     case 0x0007:		/* mul.l Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_mull_T0_T1();
 	return;
     case 0x200f:		/* muls.w Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
 	tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
 	tcg_gen_ext16s_i32(cpu_T[1], cpu_T[1]);
 	gen_op_mulsw_T0_T1();
 	return;
     case 0x200e:		/* mulu.w Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
 	gen_op_muluw_T0_T1();
 	return;
     case 0x600b:		/* neg Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_neg_T0();
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x600a:		/* negc Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_negc_T0();
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x6007:		/* not Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_not_T0();
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x200b:		/* or Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_or_T0_rN(REG(B11_8));
 	return;
     case 0x400c:		/* shad Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_shad_T0_T1();
-	gen_movl_T_rN(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
 	return;
     case 0x400d:		/* shld Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_shld_T0_T1();
-	gen_movl_T_rN(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
 	return;
     case 0x3008:		/* sub Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_sub_T0_rN(REG(B11_8));
 	return;
     case 0x300a:		/* subc Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_subc_T0_T1();
-	gen_movl_T_rN(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
 	return;
     case 0x300b:		/* subv Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_subv_T0_T1();
-	gen_movl_T_rN(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
 	return;
     case 0x2008:		/* tst Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_tst_T0_T1();
 	return;
     case 0x200a:		/* xor Rm,Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_xor_T0_rN(REG(B11_8));
 	return;
     case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
@@ -714,33 +716,33 @@ void _decode_opc(DisasContext * ctx)
     case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
 	if (ctx->fpscr & FPSCR_SZ) {
 	    gen_op_fmov_drN_DT0(XREG(B7_4));
-	    gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	    tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	    gen_op_stfq_DT0_T1(ctx);
 	} else {
 	    gen_op_fmov_frN_FT0(FREG(B7_4));
-	    gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	    tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	    gen_op_stfl_FT0_T1(ctx);
 	}
 	return;
     case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
 	if (ctx->fpscr & FPSCR_SZ) {
-	    gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	    tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	    gen_op_ldfq_T0_DT0(ctx);
 	    gen_op_fmov_DT0_drN(XREG(B11_8));
 	} else {
-	    gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	    tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	    gen_op_ldfl_T0_FT0(ctx);
 	    gen_op_fmov_FT0_frN(FREG(B11_8));
 	}
 	return;
     case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
 	if (ctx->fpscr & FPSCR_SZ) {
-	    gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	    tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	    gen_op_ldfq_T0_DT0(ctx);
 	    gen_op_fmov_DT0_drN(XREG(B11_8));
 	    gen_op_inc8_rN(REG(B7_4));
 	} else {
-	    gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	    tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	    gen_op_ldfl_T0_FT0(ctx);
 	    gen_op_fmov_FT0_frN(FREG(B11_8));
 	    gen_op_inc4_rN(REG(B7_4));
@@ -750,14 +752,14 @@ void _decode_opc(DisasContext * ctx)
 	if (ctx->fpscr & FPSCR_SZ) {
 	    gen_op_dec8_rN(REG(B11_8));
 	    gen_op_fmov_drN_DT0(XREG(B7_4));
-	    gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	    tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	    gen_op_inc8_rN(REG(B11_8));
 	    gen_op_stfq_DT0_T1(ctx);
 	    gen_op_dec8_rN(REG(B11_8));
 	} else {
 	    gen_op_dec4_rN(REG(B11_8));
 	    gen_op_fmov_frN_FT0(FREG(B7_4));
-	    gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	    tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	    gen_op_inc4_rN(REG(B11_8));
 	    gen_op_stfl_FT0_T1(ctx);
 	    gen_op_dec4_rN(REG(B11_8));
@@ -765,12 +767,12 @@ void _decode_opc(DisasContext * ctx)
 	return;
     case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
 	if (ctx->fpscr & FPSCR_SZ) {
-	    gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	    tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	    gen_op_add_rN_T0(REG(0));
 	    gen_op_ldfq_T0_DT0(ctx);
 	    gen_op_fmov_DT0_drN(XREG(B11_8));
 	} else {
-	    gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	    tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	    gen_op_add_rN_T0(REG(0));
 	    gen_op_ldfl_T0_FT0(ctx);
 	    gen_op_fmov_FT0_frN(FREG(B11_8));
@@ -779,12 +781,12 @@ void _decode_opc(DisasContext * ctx)
     case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
 	if (ctx->fpscr & FPSCR_SZ) {
 	    gen_op_fmov_drN_DT0(XREG(B7_4));
-	    gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	    tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	    gen_op_add_rN_T1(REG(0));
 	    gen_op_stfq_DT0_T1(ctx);
 	} else {
 	    gen_op_fmov_frN_FT0(FREG(B7_4));
-	    gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	    tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	    gen_op_add_rN_T1(REG(0));
 	    gen_op_stfl_FT0_T1(ctx);
 	}
@@ -841,7 +843,7 @@ void _decode_opc(DisasContext * ctx)
 	gen_op_and_imm_rN(B7_0, REG(0));
 	return;
     case 0xcd00:		/* and.b #imm,@(R0,GBR) */
-	gen_movl_rN_T(cpu_T[0], REG(0));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
 	gen_op_addl_GBR_T0();
 	tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
 	gen_op_ldub_T0_T0(ctx);
@@ -871,81 +873,81 @@ void _decode_opc(DisasContext * ctx)
 	ctx->flags |= DELAY_SLOT_CONDITIONAL;
 	return;
     case 0x8800:		/* cmp/eq #imm,R0 */
-	gen_movl_rN_T(cpu_T[0], REG(0));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
 	gen_op_cmp_eq_imm_T0(B7_0s);
 	return;
     case 0xc400:		/* mov.b @(disp,GBR),R0 */
 	gen_op_stc_gbr_T0();
 	gen_op_addl_imm_T0(B7_0);
 	gen_op_ldb_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(0));
+	tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
 	return;
     case 0xc500:		/* mov.w @(disp,GBR),R0 */
 	gen_op_stc_gbr_T0();
 	gen_op_addl_imm_T0(B7_0 * 2);
 	gen_op_ldw_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(0));
+	tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
 	return;
     case 0xc600:		/* mov.l @(disp,GBR),R0 */
 	gen_op_stc_gbr_T0();
 	gen_op_addl_imm_T0(B7_0 * 4);
 	gen_op_ldl_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(0));
+	tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
 	return;
     case 0xc000:		/* mov.b R0,@(disp,GBR) */
 	gen_op_stc_gbr_T0();
 	gen_op_addl_imm_T0(B7_0);
 	tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
-	gen_movl_rN_T(cpu_T[0], REG(0));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
 	gen_op_stb_T0_T1(ctx);
 	return;
     case 0xc100:		/* mov.w R0,@(disp,GBR) */
 	gen_op_stc_gbr_T0();
 	gen_op_addl_imm_T0(B7_0 * 2);
 	tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
-	gen_movl_rN_T(cpu_T[0], REG(0));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
 	gen_op_stw_T0_T1(ctx);
 	return;
     case 0xc200:		/* mov.l R0,@(disp,GBR) */
 	gen_op_stc_gbr_T0();
 	gen_op_addl_imm_T0(B7_0 * 4);
 	tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
-	gen_movl_rN_T(cpu_T[0], REG(0));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
 	gen_op_stl_T0_T1(ctx);
 	return;
     case 0x8000:		/* mov.b R0,@(disp,Rn) */
-	gen_movl_rN_T(cpu_T[0], REG(0));
-	gen_movl_rN_T(cpu_T[1], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B7_4)]);
 	gen_op_addl_imm_T1(B3_0);
 	gen_op_stb_T0_T1(ctx);
 	return;
     case 0x8100:		/* mov.w R0,@(disp,Rn) */
-	gen_movl_rN_T(cpu_T[0], REG(0));
-	gen_movl_rN_T(cpu_T[1], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B7_4)]);
 	gen_op_addl_imm_T1(B3_0 * 2);
 	gen_op_stw_T0_T1(ctx);
 	return;
     case 0x8400:		/* mov.b @(disp,Rn),R0 */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_addl_imm_T0(B3_0);
 	gen_op_ldb_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(0));
+	tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
 	return;
     case 0x8500:		/* mov.w @(disp,Rn),R0 */
-	gen_movl_rN_T(cpu_T[0], REG(B7_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
 	gen_op_addl_imm_T0(B3_0 * 2);
 	gen_op_ldw_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], REG(0));
+	tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
 	return;
     case 0xc700:		/* mova @(disp,PC),R0 */
-	gen_movl_imm_rN(((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3,
-			   REG(0));
+	tcg_gen_movi_i32(cpu_gregs[REG(0)],
+			 ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3);
 	return;
     case 0xcb00:		/* or #imm,R0 */
 	gen_op_or_imm_rN(B7_0, REG(0));
 	return;
     case 0xcf00:		/* or.b #imm,@(R0,GBR) */
-	gen_movl_rN_T(cpu_T[0], REG(0));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
 	gen_op_addl_GBR_T0();
 	tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
 	gen_op_ldub_T0_T0(ctx);
@@ -961,7 +963,7 @@ void _decode_opc(DisasContext * ctx)
 	gen_op_tst_imm_rN(B7_0, REG(0));
 	return;
     case 0xcc00:		/* tst.b #imm,@(R0,GBR) */
-	gen_movl_rN_T(cpu_T[0], REG(0));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
 	gen_op_addl_GBR_T0();
 	gen_op_ldub_T0_T0(ctx);
 	gen_op_tst_imm_T0(B7_0);
@@ -970,7 +972,7 @@ void _decode_opc(DisasContext * ctx)
 	gen_op_xor_imm_rN(B7_0, REG(0));
 	return;
     case 0xce00:		/* xor.b #imm,@(R0,GBR) */
-	gen_movl_rN_T(cpu_T[0], REG(0));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
 	gen_op_addl_GBR_T0();
 	tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
 	gen_op_ldub_T0_T0(ctx);
@@ -981,23 +983,23 @@ void _decode_opc(DisasContext * ctx)
 
     switch (ctx->opcode & 0xf08f) {
     case 0x408e:		/* ldc Rm,Rn_BANK */
-	gen_movl_rN_T(cpu_T[0], REG(B11_8));
-	gen_movl_T_rN(cpu_T[0], ALTREG(B6_4));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
+	tcg_gen_mov_i32(cpu_gregs[ALTREG(B6_4)], cpu_T[0]);
 	return;
     case 0x4087:		/* ldc.l @Rm+,Rn_BANK */
-	gen_movl_rN_T(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
 	gen_op_ldl_T0_T0(ctx);
-	gen_movl_T_rN(cpu_T[0], ALTREG(B6_4));
+	tcg_gen_mov_i32(cpu_gregs[ALTREG(B6_4)], cpu_T[0]);
 	gen_op_inc4_rN(REG(B11_8));
 	return;
     case 0x0082:		/* stc Rm_BANK,Rn */
-	gen_movl_rN_T(cpu_T[0], ALTREG(B6_4));
-	gen_movl_T_rN(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[ALTREG(B6_4)]);
+	tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
 	return;
     case 0x4083:		/* stc.l Rm_BANK,@-Rn */
 	gen_op_dec4_rN(REG(B11_8));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
-	gen_movl_rN_T(cpu_T[0], ALTREG(B6_4));
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[ALTREG(B6_4)]);
 	gen_op_inc4_rN(REG(B11_8));
 	gen_op_stl_T0_T1(ctx);
 	gen_op_dec4_rN(REG(B11_8));
@@ -1006,48 +1008,48 @@ void _decode_opc(DisasContext * ctx)
 
     switch (ctx->opcode & 0xf0ff) {
     case 0x0023:		/* braf Rn */
-	CHECK_NOT_DELAY_SLOT gen_movl_rN_T(cpu_T[0], REG(B11_8));
+	CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
 	gen_op_braf_T0(ctx->pc + 4);
 	ctx->flags |= DELAY_SLOT;
 	ctx->delayed_pc = (uint32_t) - 1;
 	return;
     case 0x0003:		/* bsrf Rn */
-	CHECK_NOT_DELAY_SLOT gen_movl_rN_T(cpu_T[0], REG(B11_8));
+	CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
 	gen_op_bsrf_T0(ctx->pc + 4);
 	ctx->flags |= DELAY_SLOT;
 	ctx->delayed_pc = (uint32_t) - 1;
 	return;
     case 0x4015:		/* cmp/pl Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
 	gen_op_cmp_pl_T0();
 	return;
     case 0x4011:		/* cmp/pz Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
 	gen_op_cmp_pz_T0();
 	return;
     case 0x4010:		/* dt Rn */
 	gen_op_dt_rN(REG(B11_8));
 	return;
     case 0x402b:		/* jmp @Rn */
-	CHECK_NOT_DELAY_SLOT gen_movl_rN_T(cpu_T[0], REG(B11_8));
+	CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
 	gen_op_jmp_T0();
 	ctx->flags |= DELAY_SLOT;
 	ctx->delayed_pc = (uint32_t) - 1;
 	return;
     case 0x400b:		/* jsr @Rn */
-	CHECK_NOT_DELAY_SLOT gen_movl_rN_T(cpu_T[0], REG(B11_8));
+	CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
 	gen_op_jsr_T0(ctx->pc + 4);
 	ctx->flags |= DELAY_SLOT;
 	ctx->delayed_pc = (uint32_t) - 1;
 	return;
 #define LDST(reg,ldnum,ldpnum,ldop,stnum,stpnum,stop,extrald)	\
   case ldnum:							\
-    gen_movl_rN_T (cpu_T[0], REG(B11_8));			\
+    tcg_gen_mov_i32 (cpu_T[0], cpu_gregs[REG(B11_8)]);		\
     gen_op_##ldop##_T0_##reg ();				\
     extrald							\
     return;							\
   case ldpnum:							\
-    gen_movl_rN_T (cpu_T[0], REG(B11_8));			\
+    tcg_gen_mov_i32 (cpu_T[0], cpu_gregs[REG(B11_8)]);		\
     gen_op_ldl_T0_T0 (ctx);					\
     gen_op_inc4_rN (REG(B11_8));				\
     gen_op_##ldop##_T0_##reg ();				\
@@ -1055,12 +1057,12 @@ void _decode_opc(DisasContext * ctx)
     return;							\
   case stnum:							\
     gen_op_##stop##_##reg##_T0 ();				\
-    gen_movl_T_rN (cpu_T[0], REG(B11_8));			\
+    tcg_gen_mov_i32 (cpu_gregs[REG(B11_8)], cpu_T[0]);		\
     return;							\
   case stpnum:							\
     gen_op_##stop##_##reg##_T0 ();				\
     gen_op_dec4_rN (REG(B11_8));				\
-    gen_movl_rN_T (cpu_T[1], REG(B11_8));			\
+    tcg_gen_mov_i32 (cpu_T[1], cpu_gregs[REG(B11_8)]);		\
     gen_op_inc4_rN (REG(B11_8));				\
     gen_op_stl_T0_T1 (ctx);					\
     gen_op_dec4_rN (REG(B11_8));				\
@@ -1079,23 +1081,23 @@ void _decode_opc(DisasContext * ctx)
 	LDST(fpscr, 0x406a, 0x4066, lds, 0x006a, 0x4062, sts, ctx->bstate =
 	     BS_STOP;)
     case 0x00c3:		/* movca.l R0,@Rm */
-	gen_movl_rN_T(cpu_T[0], REG(0));
-	gen_movl_rN_T(cpu_T[1], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
+	tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
 	gen_op_stl_T0_T1(ctx);
 	return;
     case 0x0029:		/* movt Rn */
 	gen_op_movt_rN(REG(B11_8));
 	return;
     case 0x0093:		/* ocbi @Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
 	gen_op_ldl_T0_T0(ctx);
 	return;
     case 0x00a3:		/* ocbp @Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
 	gen_op_ldl_T0_T0(ctx);
 	return;
     case 0x00b3:		/* ocbwb @Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
 	gen_op_ldl_T0_T0(ctx);
 	return;
     case 0x0083:		/* pref @Rn */
@@ -1141,7 +1143,7 @@ void _decode_opc(DisasContext * ctx)
 	gen_op_shlr16_Rn(REG(B11_8));
 	return;
     case 0x401b:		/* tas.b @Rn */
-	gen_movl_rN_T(cpu_T[0], REG(B11_8));
+	tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
 	tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
 	gen_op_ldub_T0_T0(ctx);
 	gen_op_cmp_eq_imm_T0(0);