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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-07-11 10:36:47 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-07-11 10:36:47 +0000 |
| commit | 3c4c9f9f51599845fba61240aba0f38485df7c14 (patch) | |
| tree | df28fd464900cdb523818d60a0f871242b520ab2 /target-ppc | |
| parent | 81442192975a7badff6c8abcd7c800ef4c552470 (diff) | |
| download | qemu-3c4c9f9f51599845fba61240aba0f38485df7c14.zip qemu-3c4c9f9f51599845fba61240aba0f38485df7c14.tar.gz qemu-3c4c9f9f51599845fba61240aba0f38485df7c14.tar.bz2 | |
Fix PPCEMB for 32bit hosts.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3059 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu.h | 2 | ||||
| -rw-r--r-- | target-ppc/exec.h | 10 |
2 files changed, 6 insertions, 6 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 57e4662..435b838 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -693,7 +693,7 @@ struct CPUPPCState { /* temporary fixed-point registers * used to emulate 64 bits target on 32 bits hosts */ - target_ulong t0, t1, t2; + ppc_gpr_t t0, t1, t2; #endif ppc_avr_t t0_avr, t1_avr, t2_avr; diff --git a/target-ppc/exec.h b/target-ppc/exec.h index ee5183e..69807ad 100644 --- a/target-ppc/exec.h +++ b/target-ppc/exec.h @@ -43,15 +43,15 @@ register unsigned long T1 asm(AREG2); register unsigned long T2 asm(AREG3); #endif /* We may, sometime, need 64 bits registers on 32 bits target */ -#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB) || (HOST_LONG_BITS == 64) -#define T0_64 T0 -#define T1_64 T1 -#define T2_64 T2 -#else +#if TARGET_GPR_BITS > HOST_LONG_BITS /* no registers can be used */ #define T0_64 (env->t0) #define T1_64 (env->t1) #define T2_64 (env->t2) +#else +#define T0_64 T0 +#define T1_64 T1 +#define T2_64 T2 #endif /* Provision for Altivec */ #define T0_avr (env->t0_avr) |