diff options
author | Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> | 2016-09-20 22:05:01 +0530 |
---|---|---|
committer | David Gibson <david@gibson.dropbear.id.au> | 2016-09-23 12:39:07 +1000 |
commit | d76ab5e1c7db5f064700b9c3cb0924ccfd9017e5 (patch) | |
tree | 02a6851b90b0fe8d6cede2dd4c0041ee416336b3 /target-ppc/mmu_helper.c | |
parent | e3cffe6fad29e07d401eabb913a6d88501d5c143 (diff) | |
download | qemu-d76ab5e1c7db5f064700b9c3cb0924ccfd9017e5.zip qemu-d76ab5e1c7db5f064700b9c3cb0924ccfd9017e5.tar.gz qemu-d76ab5e1c7db5f064700b9c3cb0924ccfd9017e5.tar.bz2 |
target-ppc: tlbie/tlbivax should have global effect
tlbie (BookS) and tlbivax (BookE) plus the H_CALLs(pseries) should have
a global effect.
Introduces TLB_NEED_GLOBAL_FLUSH flag. During lazy tlb flush, after
taking care of pending local flushes, check broadcast flush(at context
synchronizing event ptesync/tlbsync, etc) is needed. Depending on the
bitmask state of the tlb_need_flush, tlb is flushed from other cpus if
needed and the flags are cleared.
Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
[dwg: Use 'true' instead of '1' for call to check_tlb_flush()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/mmu_helper.c')
-rw-r--r-- | target-ppc/mmu_helper.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 0124150..d09fc0a 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -2757,7 +2757,7 @@ static inline void booke206_invalidate_ea_tlb(CPUPPCState *env, int tlbn, void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + CPUState *cs; if (address & 0x4) { /* flush all entries */ @@ -2774,11 +2774,15 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) if (address & 0x8) { /* flush TLB1 entries */ booke206_invalidate_ea_tlb(env, 1, address); - tlb_flush(CPU(cpu), 1); + CPU_FOREACH(cs) { + tlb_flush(cs, 1); + } } else { /* flush TLB0 entries */ booke206_invalidate_ea_tlb(env, 0, address); - tlb_flush_page(CPU(cpu), address & MAS2_EPN_MASK); + CPU_FOREACH(cs) { + tlb_flush_page(cs, address & MAS2_EPN_MASK); + } } } |