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authorPeter Maydell <peter.maydell@linaro.org>2016-06-07 12:54:25 +0100
committerPeter Maydell <peter.maydell@linaro.org>2016-06-07 12:54:25 +0100
commit0601d6a4112a5b0333d2348aa2c3465cc0075ec6 (patch)
tree5ffd5808261948ec27f3160aece62acc7c20ddcb /target-ppc/excp_helper.c
parent76462405809d29bab65a3699686998ba124ab942 (diff)
parent4d6a0680fa425230748a2d91d81be9afe050eeb3 (diff)
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160607' into staging
ppc patch queue for 2016-05-31 Latest patch queue for ppc. Several significant things in here: * A bunch of patches from BenH fixing things in TCG - This should fix several regressions introduced by recent patches for better HV mode support - It also fixes some other bugs discovered along the way * Some fixes and cleanups for Mac machine types from Marc Cave-Ayland * Preliminary patches towards dynamic DMA window support from Alexey Kardashevskiy - This includes a patch to migration code code * Increase number of hotpluggable memory slots - Includes a change to KVM generic code, ACKed by Paolo * Another TCG fix for an SPE instruction # gpg: Signature made Tue 07 Jun 2016 11:46:57 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.7-20160607: (26 commits) ppc: Do not take exceptions on unknown SPRs in privileged mode ppc: Add missing slbfee. instruction on ppc64 BookS processors ppc: Fix slbia decode ppc: Fix mtmsr decoding ppc: POWER7 has lq/stq instructions and stq need to check ISA ppc: POWER7 had ACOP and PID registers ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors ppc: Properly tag the translation cache based on MMU mode dbdma: use DMA memory interface for memory accesses macio: use DMA memory interface for non-block ATAPI transfers target-ppc: fixup bitrot in mmu_helper.c debug statements spapr_pci: Drop cannot_instantiate_with_device_add_yet=false ppc: fix hrfid, tlbia and slbia privilege ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV ppc: Better figure out if processor has HV mode spapr: Introduce pseries-2.7 machine type spapr: Increase hotpluggable memory slots to 256 spapr_pci: Add and export DMA resetting helper spapr_pci: Reset DMA config on PHB reset ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-ppc/excp_helper.c')
-rw-r--r--target-ppc/excp_helper.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index a37009e..30e960e 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -709,8 +709,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
}
}
#endif
- /* XXX: we don't use hreg_store_msr here as already have treated
- * any special case that could occur. Just store MSR and update hflags
+ /* We don't use hreg_store_msr here as already have treated
+ * any special case that could occur. Just store MSR and update hflags
+ *
+ * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
+ * will prevent setting of the HV bit which some exceptions might need
+ * to do.
*/
env->msr = new_msr & env->msr_mask;
hreg_compute_hflags(env);