diff options
| author | Andreas Färber <afaerber@suse.de> | 2013-08-26 08:31:06 +0200 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2014-03-13 19:20:46 +0100 |
| commit | 27103424c40ce71053c07d8a54ef431365fa9b7f (patch) | |
| tree | bec190ce2f52c17d5f5963d743f6c64af47c9240 /target-openrisc | |
| parent | 6f03bef0ffc5cd75ac5ffcca0383c489ae48108c (diff) | |
| download | qemu-27103424c40ce71053c07d8a54ef431365fa9b7f.zip qemu-27103424c40ce71053c07d8a54ef431365fa9b7f.tar.gz qemu-27103424c40ce71053c07d8a54ef431365fa9b7f.tar.bz2 | |
cpu: Move exception_index field from CPU_COMMON to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-openrisc')
| -rw-r--r-- | target-openrisc/cpu.c | 2 | ||||
| -rw-r--r-- | target-openrisc/exception.c | 4 | ||||
| -rw-r--r-- | target-openrisc/interrupt.c | 12 | ||||
| -rw-r--r-- | target-openrisc/mmu.c | 3 |
4 files changed, 12 insertions, 9 deletions
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 99e4aa7..b601de0 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -48,7 +48,7 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.pc = 0x100; cpu->env.sr = SR_FO | SR_SM; - cpu->env.exception_index = -1; + s->exception_index = -1; cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S; diff --git a/target-openrisc/exception.c b/target-openrisc/exception.c index 58e53c6..b96f3f8 100644 --- a/target-openrisc/exception.c +++ b/target-openrisc/exception.c @@ -22,6 +22,8 @@ void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp) { - cpu->env.exception_index = excp; + CPUState *cs = CPU(cpu); + + cs->exception_index = excp; cpu_loop_exit(&cpu->env); } diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index 2153e7e..087e2f1 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -27,9 +27,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) { +#ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = &cpu->env; -#ifndef CONFIG_USER_ONLY env->epcr = env->pc; if (env->flags & D_FLAG) { @@ -37,7 +37,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr |= SR_DSX; env->epcr -= 4; } - if (env->exception_index == EXCP_SYSCALL) { + if (cs->exception_index == EXCP_SYSCALL) { env->epcr += 4; } @@ -54,12 +54,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; - if (env->exception_index > 0 && env->exception_index < EXCP_NR) { - env->pc = (env->exception_index << 8); + if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { + env->pc = (cs->exception_index << 8); } else { - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); } #endif - env->exception_index = -1; + cs->exception_index = -1; } diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c index 1fd0a0a..4222219 100644 --- a/target-openrisc/mmu.c +++ b/target-openrisc/mmu.c @@ -139,6 +139,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, int rw, int tlb_error) { + CPUState *cs = CPU(cpu); int exception = 0; switch (tlb_error) { @@ -169,7 +170,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, #endif } - cpu->env.exception_index = exception; + cs->exception_index = exception; cpu->env.eear = address; } |