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author | Andreas Färber <afaerber@suse.de> | 2013-07-07 12:40:38 +0200 |
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committer | Andreas Färber <afaerber@suse.de> | 2013-07-27 00:04:01 +0200 |
commit | 30028739eb6b2e95b94b957f3b4f8f258da3aa88 (patch) | |
tree | 5c21bc0331694ac305fa5ecdff83283ee3a48296 /target-openrisc/gdbstub.c | |
parent | 814ac26c2d3820b85f05b696735d4e1e6d7d05aa (diff) | |
download | qemu-30028739eb6b2e95b94b957f3b4f8f258da3aa88.zip qemu-30028739eb6b2e95b94b957f3b4f8f258da3aa88.tar.gz qemu-30028739eb6b2e95b94b957f3b4f8f258da3aa88.tar.bz2 |
target-openrisc: Move cpu_gdb_{read,write}_register()
Reviewed-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-openrisc/gdbstub.c')
-rw-r--r-- | target-openrisc/gdbstub.c | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/target-openrisc/gdbstub.c b/target-openrisc/gdbstub.c new file mode 100644 index 0000000..fba096a --- /dev/null +++ b/target-openrisc/gdbstub.c @@ -0,0 +1,77 @@ +/* + * OpenRISC gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ + +static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + GET_REG32(env->gpr[n]); + } else { + switch (n) { + case 32: /* PPC */ + GET_REG32(env->ppc); + + case 33: /* NPC */ + GET_REG32(env->npc); + + case 34: /* SR */ + GET_REG32(env->sr); + + default: + break; + } + } + return 0; +} + +static int cpu_gdb_write_register(CPUOpenRISCState *env, + uint8_t *mem_buf, int n) +{ + OpenRISCCPU *cpu = openrisc_env_get_cpu(env); + CPUClass *cc = CPU_GET_CLASS(cpu); + uint32_t tmp; + + if (n > cc->gdb_num_core_regs) { + return 0; + } + + tmp = ldl_p(mem_buf); + + if (n < 32) { + env->gpr[n] = tmp; + } else { + switch (n) { + case 32: /* PPC */ + env->ppc = tmp; + break; + + case 33: /* NPC */ + env->npc = tmp; + break; + + case 34: /* SR */ + env->sr = tmp; + break; + + default: + break; + } + } + return 4; +} |