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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2006-10-23 21:25:11 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2006-10-23 21:25:11 +0000
commitdd016883fb560f0dc541d4da829caa33830fd30d (patch)
tree3298f636f50927f2caf0b6956f796cefaf665fee /target-mips
parentd37aca662561a54a5ea177c6c05280633fa41cb8 (diff)
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add support for cvt.s.d and cvt.d.s (Aurelien Jarno)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2198 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/op.c12
-rw-r--r--target-mips/translate.c14
2 files changed, 26 insertions, 0 deletions
diff --git a/target-mips/op.c b/target-mips/op.c
index 4575517..39db3ce 100644
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -785,12 +785,24 @@ void op_mtc1 (void)
#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
+FLOAT_OP(cvtd, s)
+{
+ FDT2 = float32_to_float64(WT0, &env->fp_status);
+ DEBUG_FPU_STATE();
+ RETURN();
+}
FLOAT_OP(cvtd, w)
{
FDT2 = int32_to_float64(WT0, &env->fp_status);
DEBUG_FPU_STATE();
RETURN();
}
+FLOAT_OP(cvts, d)
+{
+ FST2 = float64_to_float32(WT0, &env->fp_status);
+ DEBUG_FPU_STATE();
+ RETURN();
+}
FLOAT_OP(cvts, w)
{
FST2 = int32_to_float32(WT0, &env->fp_status);
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 7ad8ebd..c0de12b 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1675,6 +1675,13 @@ static void gen_farith (DisasContext *ctx, int fmt, int ft, int fs, int fd, int
GEN_STORE_FTN_FREG(fd, WT2);
opn = "ceil.w.d";
break;
+ case FOP(33, 16): /* cvt.d.s */
+ CHECK_FR(ctx, fs | fd);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ gen_op_float_cvtd_s();
+ GEN_STORE_FTN_FREG(fd, DT2);
+ opn = "cvt.d.s";
+ break;
case FOP(33, 20): /* cvt.d.w */
CHECK_FR(ctx, fs | fd);
GEN_LOAD_FREG_FTN(WT0, fs);
@@ -1782,6 +1789,13 @@ static void gen_farith (DisasContext *ctx, int fmt, int ft, int fs, int fd, int
GEN_STORE_FTN_FREG(fd, WT2);
opn = "trunc.w.s";
break;
+ case FOP(32, 17): /* cvt.s.d */
+ CHECK_FR(ctx, fs | fd);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ gen_op_float_cvts_d();
+ GEN_STORE_FTN_FREG(fd, WT2);
+ opn = "cvt.s.d";
+ break;
case FOP(32, 20): /* cvt.s.w */
CHECK_FR(ctx, fs | fd);
GEN_LOAD_FREG_FTN(WT0, fs);