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authorAndreas Färber <afaerber@suse.de>2013-08-27 00:28:06 +0200
committerAndreas Färber <afaerber@suse.de>2014-03-13 19:20:47 +0100
commitd5a11fefef1eeed86a8f06021067ba9990729a5a (patch)
tree7a99e0676de042609104c21d98ff2a94be017c9a /target-mips
parentf0c3c505a8ec1a948006b3a16a35864a2270a84b (diff)
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exec: Change tlb_fill() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/op_helper.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 5a4a656..8c050fc 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2145,15 +2145,16 @@ static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
}
-void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- MIPSCPU *cpu = mips_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
int ret;
ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
do_raise_exception_err(env, cs->exception_index,
env->error_code, retaddr);
}