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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-22 21:54:00 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-22 21:54:00 +0000
commitcb2c9921f851b5cb54c188106800331ab172ba78 (patch)
tree940463477e7cdbc6bbb02fee038b4cc995c7a025 /target-mips
parent28de16da38f20b3fe76fa80d10561c3a998342e2 (diff)
downloadqemu-cb2c9921f851b5cb54c188106800331ab172ba78.zip
qemu-cb2c9921f851b5cb54c188106800331ab172ba78.tar.gz
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Use concet TCG instructions in the MIPS target.
Signed-off-by: Thiemo Seufer <ths@networkno.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5303 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/translate.c28
1 files changed, 4 insertions, 24 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 3ac0f60..ec375e1 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -2129,7 +2129,6 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
{
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
tcg_gen_ext32s_tl(t0, t0);
tcg_gen_ext32s_tl(t1, t1);
@@ -2138,11 +2137,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
gen_load_LO(t0, 0);
gen_load_HI(t1, 0);
- tcg_gen_extu_tl_i64(r_tmp2, t0);
- tcg_gen_extu_tl_i64(r_tmp3, t1);
- tcg_gen_shli_i64(r_tmp3, r_tmp3, 32);
- tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3);
- tcg_temp_free(r_tmp3);
+ tcg_gen_concat_tl_i64(r_tmp2, t0, t1);
tcg_gen_add_i64(r_tmp1, r_tmp1, r_tmp2);
tcg_temp_free(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);
@@ -2160,7 +2155,6 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
{
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
@@ -2169,11 +2163,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
gen_load_LO(t0, 0);
gen_load_HI(t1, 0);
- tcg_gen_extu_tl_i64(r_tmp2, t0);
- tcg_gen_extu_tl_i64(r_tmp3, t1);
- tcg_gen_shli_i64(r_tmp3, r_tmp3, 32);
- tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3);
- tcg_temp_free(r_tmp3);
+ tcg_gen_concat_tl_i64(r_tmp2, t0, t1);
tcg_gen_add_i64(r_tmp1, r_tmp1, r_tmp2);
tcg_temp_free(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);
@@ -2191,7 +2181,6 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
{
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
tcg_gen_ext32s_tl(t0, t0);
tcg_gen_ext32s_tl(t1, t1);
@@ -2200,11 +2189,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
gen_load_LO(t0, 0);
gen_load_HI(t1, 0);
- tcg_gen_extu_tl_i64(r_tmp2, t0);
- tcg_gen_extu_tl_i64(r_tmp3, t1);
- tcg_gen_shli_i64(r_tmp3, r_tmp3, 32);
- tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3);
- tcg_temp_free(r_tmp3);
+ tcg_gen_concat_tl_i64(r_tmp2, t0, t1);
tcg_gen_sub_i64(r_tmp1, r_tmp1, r_tmp2);
tcg_temp_free(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);
@@ -2222,7 +2207,6 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
{
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
@@ -2231,11 +2215,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
gen_load_LO(t0, 0);
gen_load_HI(t1, 0);
- tcg_gen_extu_tl_i64(r_tmp2, t0);
- tcg_gen_extu_tl_i64(r_tmp3, t1);
- tcg_gen_shli_i64(r_tmp3, r_tmp3, 32);
- tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3);
- tcg_temp_free(r_tmp3);
+ tcg_gen_concat_tl_i64(r_tmp2, t0, t1);
tcg_gen_sub_i64(r_tmp1, r_tmp1, r_tmp2);
tcg_temp_free(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);