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authorDongxue Zhang <elta.era@gmail.com>2014-07-29 21:48:10 +0800
committerLeon Alrae <leon.alrae@imgtec.com>2014-10-14 13:29:14 +0100
commita83bddd60de0dfdbc04c6683c2701682073af5cf (patch)
tree725f1149424e69ff01677bc8d372cacaf6822e39 /target-mips
parenta773cc7970432d1bad3835f3112512cabad3f367 (diff)
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target-mips/translate.c: Update OPC_SYNCI
Update OPC_SYNCI with BS_STOP, in order to handle the instructions which saved in the same TB of the store instruction. Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: update microMIPS SYNCI as well] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/translate.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 57c2d41..7b9e8cd 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -13190,6 +13190,9 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
gen_logic_imm(ctx, OPC_LUI, rs, -1, imm);
break;
case SYNCI:
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->bstate = BS_STOP;
break;
case BC2F:
case BC2T:
@@ -16928,7 +16931,9 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SYNCI:
check_insn(ctx, ISA_MIPS32R2);
- /* Treat as NOP. */
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->bstate = BS_STOP;
break;
case OPC_BPOSGE32: /* MIPS DSP branch */
#if defined(TARGET_MIPS64)