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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-11-11 11:50:51 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-11-11 11:50:51 +0000
commita6e92a658b99b4ab3b19b2f32352005e6190556f (patch)
tree25c49d5c08eafee457d2f0b14188e887ae9f3afb /target-mips
parent9bf3eb2ca542dd9306cb2e72fc68e02ba3e56e2e (diff)
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target-mips: gen_compute_branch1()
Optimize code generation in gen_compute_branch1(): - Directly use I32 variables instead of converting values from _tl to _i32 and back to _tl. - Write the result directly to bcond instead of passing by a local variable. - Temp variables are valid up to and *including* the brcond instruction. Use them instead of temp local variables. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5684 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/translate.c122
1 files changed, 41 insertions, 81 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 0ce7f5f..386e0e3 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5634,8 +5634,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
target_ulong btarget;
const char *opn = "cp1 cond branch";
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
- TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
if (cc != 0)
check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
@@ -5647,19 +5646,14 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_not_tl(t0, t0);
- tcg_gen_movi_tl(t1, 0x1 << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0x1 << cc);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1f";
@@ -5668,19 +5662,14 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_not_tl(t0, t0);
- tcg_gen_movi_tl(t1, 0x1 << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0x1 << cc);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1fl";
@@ -5689,18 +5678,14 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_movi_tl(t1, 0x1 << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0x1 << cc);
+ tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1t";
@@ -5709,42 +5694,32 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_movi_tl(t1, 0x1 << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0x1 << cc);
+ tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1tl";
likely:
ctx->hflags |= MIPS_HFLAG_BL;
- tcg_gen_trunc_tl_i32(bcond, t0);
break;
case OPC_BC1FANY2:
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_not_tl(t0, t0);
- tcg_gen_movi_tl(t1, 0x3 << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0x3 << cc);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1any2f";
@@ -5753,18 +5728,14 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_movi_tl(t1, 0x3 << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0x3 << cc);
+ tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1any2t";
@@ -5773,19 +5744,14 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_not_tl(t0, t0);
- tcg_gen_movi_tl(t1, 0xf << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0xf << cc);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1any4f";
@@ -5794,24 +5760,19 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_movi_tl(t1, 0xf << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0xf << cc);
+ tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1any4t";
not_likely:
ctx->hflags |= MIPS_HFLAG_BC;
- tcg_gen_trunc_tl_i32(bcond, t0);
break;
default:
MIPS_INVAL(opn);
@@ -5824,7 +5785,6 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
out:
tcg_temp_free(t0);
- tcg_temp_free(t1);
}
/* Coprocessor 1 (FPU) */