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author | Stefan Weil <sw@weilnetz.de> | 2012-04-07 09:23:39 +0200 |
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committer | Blue Swirl <blauwirbel@gmail.com> | 2012-04-07 14:00:45 +0000 |
commit | 5cbdb3a34bce4ee64dd203cfd74979409fa3d51e (patch) | |
tree | 4b59207391a065bd438f3c30219ec562c4ec80de /target-mips | |
parent | c5ec15ea3b9374e6d493f8de7dfc170cec058068 (diff) | |
download | qemu-5cbdb3a34bce4ee64dd203cfd74979409fa3d51e.zip qemu-5cbdb3a34bce4ee64dd203cfd74979409fa3d51e.tar.gz qemu-5cbdb3a34bce4ee64dd203cfd74979409fa3d51e.tar.bz2 |
Replace Qemu by QEMU in comments
The official spelling is QEMU.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
[blauwirbel@gmail.com: fixed comment style in hw/sun4m.c]
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-mips')
-rw-r--r-- | target-mips/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 7430aa5..257c4c4 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -418,7 +418,7 @@ struct CPUMIPSState { /* We waste some space so we can handle shadow registers like TCs. */ TCState tcs[MIPS_SHADOW_SET_MAX]; CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; - /* Qemu */ + /* QEMU */ int error_code; uint32_t hflags; /* CPU State */ /* TMASK defines different execution modes */ |