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authorbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-25 18:11:30 +0000
committerbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-25 18:11:30 +0000
commite737b32a3688d415c3b1f9d0a3fb2b941b1e758c (patch)
tree821be1b667f4d9430bbb89af4697b99536b0ce98 /target-i386
parentc5096daf7f5e6d8a607319fbd1dfa8acbe96f4b8 (diff)
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Core 2 Duo specification (Alexander Graf).
This patch adds a Core 2 Duo CPU to the available CPU types. The CPU definition tries to resemble a real CPU as good as possible, whilst not exposing features qemu does not implement. The patch also includes some minor additions that Core 2 Duo CPUs have: - New MSR: MSR_IA32_PERF_STATUS - CPUID up to level 5 (cache info and mwait) Signed-off-by: Alexander Graf <agraf@suse.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5317 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386')
-rw-r--r--target-i386/cpu.h5
-rw-r--r--target-i386/helper.c18
-rw-r--r--target-i386/op_helper.c43
3 files changed, 66 insertions, 0 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index dd57abc..d1deda7 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -242,6 +242,8 @@
#define MSR_MCG_STATUS 0x17a
#define MSR_MCG_CTL 0x17b
+#define MSR_IA32_PERF_STATUS 0x198
+
#define MSR_PAT 0x277
#define MSR_EFER 0xc0000080
@@ -341,6 +343,9 @@
#define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
#define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
+#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */
+#define CPUID_MWAIT_EMX (0 << 1) /* enumeration supported */
+
#define EXCP00_DIVZ 0
#define EXCP01_SSTP 1
#define EXCP02_NMI 2
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 2dae1e3..f7ad584 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -165,6 +165,24 @@ static x86_def_t x86_defs[] = {
.xlevel = 0x8000000A,
.model_id = "QEMU Virtual CPU version " QEMU_VERSION,
},
+ {
+ .name = "core2duo",
+ /* original is on level 10 */
+ .level = 5,
+ .family = 6,
+ .model = 15,
+ .stepping = 11,
+ /* the original CPU does have many more features that are
+ * not implemented yet */
+ .features = PPRO_FEATURES |
+ CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
+ CPUID_PSE36,
+ .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
+ .ext2_features = (PPRO_FEATURES & 0x0183F3FF) |
+ CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
+ .xlevel = 0x8000000A,
+ .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
+ },
#endif
{
.name = "qemu32",
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index 23f3080..c423ca0 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -1919,6 +1919,43 @@ void helper_cpuid(void)
ECX = 0;
EDX = 0x2c307d;
break;
+ case 4:
+ /* cache info: needed for Core compatibility */
+ switch (ECX) {
+ case 0: /* L1 dcache info */
+ EAX = 0x0000121;
+ EBX = 0x1c0003f;
+ ECX = 0x000003f;
+ EDX = 0x0000001;
+ break;
+ case 1: /* L1 icache info */
+ EAX = 0x0000122;
+ EBX = 0x1c0003f;
+ ECX = 0x000003f;
+ EDX = 0x0000001;
+ break;
+ case 2: /* L2 cache info */
+ EAX = 0x0000143;
+ EBX = 0x3c0003f;
+ ECX = 0x0000fff;
+ EDX = 0x0000001;
+ break;
+ default: /* end of info */
+ EAX = 0;
+ EBX = 0;
+ ECX = 0;
+ EDX = 0;
+ break;
+ }
+
+ break;
+ case 5:
+ /* mwait info: needed for Core compatibility */
+ EAX = 0; /* Smallest monitor-line size in bytes */
+ EBX = 0; /* Largest monitor-line size in bytes */
+ ECX = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
+ EDX = 0;
+ break;
case 0x80000000:
EAX = env->cpuid_xlevel;
EBX = env->cpuid_vendor1;
@@ -3089,6 +3126,12 @@ void helper_wrmsr(void)
case MSR_VM_HSAVE_PA:
env->vm_hsave = val;
break;
+ case MSR_IA32_PERF_STATUS:
+ /* tsc_increment_by_tick */
+ val = 1000ULL;
+ /* CPU multiplier */
+ val |= (((uint64_t)4ULL) << 40);
+ break;
#ifdef TARGET_X86_64
case MSR_LSTAR:
env->lstar = val;