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authorNitin A Kamble <nitin.a.kamble@intel.com>2009-06-04 14:29:50 -0700
committerAnthony Liguori <aliguori@us.ibm.com>2009-06-16 15:36:47 -0500
commit538f368612565f7c7672145c31e87f1d3d02d545 (patch)
tree4629daba49a0070d1ed9130a0146a5c99e8819dd /target-i386
parentef7681389f1d5bd4bba9b66504df8a0b768b27b1 (diff)
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QEMU KVM: i386: Fix the cpu reset state
As per the IA32 processor manual, the accessed bit is set to 1 in the processor state after reset. qemu pc cpu_reset code was missing this accessed bit setting. Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'target-i386')
-rw-r--r--target-i386/helper.c18
1 files changed, 12 insertions, 6 deletions
diff --git a/target-i386/helper.c b/target-i386/helper.c
index b7b101b..75e7ccd 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -496,17 +496,23 @@ void cpu_reset(CPUX86State *env)
env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
- DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK);
+ DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
+ DESC_R_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
- DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
+ DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
+ DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
- DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
+ DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
+ DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
- DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
+ DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
+ DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
- DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
+ DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
+ DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
- DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
+ DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
+ DESC_A_MASK);
env->eip = 0xfff0;
env->regs[R_EDX] = env->cpuid_version;