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| author | Richard Henderson <rth@twiddle.net> | 2014-02-24 14:59:54 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2014-02-28 08:44:01 -0800 |
| commit | 4e47e39ab0ded72c0af174131ecf49d588d66c12 (patch) | |
| tree | 678d24cda64ee50b354571babe8eca5806529201 /target-i386 | |
| parent | d2fe51bda8adf33d07c21e034fdc13a1e1fa4e19 (diff) | |
| download | qemu-4e47e39ab0ded72c0af174131ecf49d588d66c12.zip qemu-4e47e39ab0ded72c0af174131ecf49d588d66c12.tar.gz qemu-4e47e39ab0ded72c0af174131ecf49d588d66c12.tar.bz2 | |
target-i386: Fix SSE status flag corruption
When we restore the mxcsr register with FXRSTOR, or set it with gdb,
we need to update the various SSE status flags in CPUX86State
Reported-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/cpu.h | 3 | ||||
| -rw-r--r-- | target-i386/fpu_helper.c | 15 | ||||
| -rw-r--r-- | target-i386/gdbstub.c | 2 |
3 files changed, 12 insertions, 8 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 1b94f0f..5d3f143 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1259,6 +1259,9 @@ static inline void cpu_load_efer(CPUX86State *env, uint64_t val) } } +/* fpu_helper.c */ +void cpu_set_mxcsr(CPUX86State *env, uint32_t val); + /* svm_helper.c */ void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, uint64_t param); diff --git a/target-i386/fpu_helper.c b/target-i386/fpu_helper.c index c0427fe..de7ba76 100644 --- a/target-i386/fpu_helper.c +++ b/target-i386/fpu_helper.c @@ -1179,7 +1179,7 @@ void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64) if (env->cr[4] & CR4_OSFXSR_MASK) { /* XXX: finish it */ - env->mxcsr = cpu_ldl_data(env, ptr + 0x18); + cpu_set_mxcsr(env, cpu_ldl_data(env, ptr + 0x18)); /* cpu_ldl_data(env, ptr + 0x1c); */ if (env->hflags & HF_CS64_MASK) { nb_xmm_regs = 16; @@ -1229,12 +1229,14 @@ floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper) #define SSE_RC_CHOP 0x6000 #define SSE_FZ 0x8000 -static void update_sse_status(CPUX86State *env) +void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) { int rnd_type; + env->mxcsr = mxcsr; + /* set rounding mode */ - switch (env->mxcsr & SSE_RC_MASK) { + switch (mxcsr & SSE_RC_MASK) { default: case SSE_RC_NEAR: rnd_type = float_round_nearest_even; @@ -1252,16 +1254,15 @@ static void update_sse_status(CPUX86State *env) set_float_rounding_mode(rnd_type, &env->sse_status); /* set denormals are zero */ - set_flush_inputs_to_zero((env->mxcsr & SSE_DAZ) ? 1 : 0, &env->sse_status); + set_flush_inputs_to_zero((mxcsr & SSE_DAZ) ? 1 : 0, &env->sse_status); /* set flush to zero */ - set_flush_to_zero((env->mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status); + set_flush_to_zero((mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status); } void helper_ldmxcsr(CPUX86State *env, uint32_t val) { - env->mxcsr = val; - update_sse_status(env); + cpu_set_mxcsr(env, val); } void helper_enter_mmx(CPUX86State *env) diff --git a/target-i386/gdbstub.c b/target-i386/gdbstub.c index 15bebef..d34e535 100644 --- a/target-i386/gdbstub.c +++ b/target-i386/gdbstub.c @@ -222,7 +222,7 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 4; case IDX_MXCSR_REG: - env->mxcsr = ldl_p(mem_buf); + cpu_set_mxcsr(env, ldl_p(mem_buf)); return 4; } } |